mirror of
https://github.com/GreemDev/Ryujinx
synced 2024-11-22 17:56:59 +01:00
80 lines
2.4 KiB
C#
80 lines
2.4 KiB
C#
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using ChocolArm64.Decoder;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Madd(AILEmitterCtx Context) => EmitMul(Context, OpCodes.Add);
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public static void Msub(AILEmitterCtx Context) => EmitMul(Context, OpCodes.Sub);
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private static void EmitMul(AILEmitterCtx Context, OpCode ILOp)
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{
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AOpCodeMul Op = (AOpCodeMul)Context.CurrOp;
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Context.EmitLdintzr(Op.Ra);
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Context.EmitLdintzr(Op.Rn);
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Context.EmitLdintzr(Op.Rm);
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Context.Emit(OpCodes.Mul);
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Context.Emit(ILOp);
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Context.EmitStintzr(Op.Rd);
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}
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public static void Smaddl(AILEmitterCtx Context) => EmitMull(Context, OpCodes.Add, true);
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public static void Smsubl(AILEmitterCtx Context) => EmitMull(Context, OpCodes.Sub, true);
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public static void Umaddl(AILEmitterCtx Context) => EmitMull(Context, OpCodes.Add, false);
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public static void Umsubl(AILEmitterCtx Context) => EmitMull(Context, OpCodes.Sub, false);
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private static void EmitMull(AILEmitterCtx Context, OpCode AddSubOp, bool Signed)
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{
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AOpCodeMul Op = (AOpCodeMul)Context.CurrOp;
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OpCode CastOp = Signed
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? OpCodes.Conv_I8
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: OpCodes.Conv_U8;
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Context.EmitLdintzr(Op.Ra);
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Context.EmitLdintzr(Op.Rn);
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Context.Emit(OpCodes.Conv_I4);
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Context.Emit(CastOp);
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Context.EmitLdintzr(Op.Rm);
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Context.Emit(OpCodes.Conv_I4);
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Context.Emit(CastOp);
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Context.Emit(OpCodes.Mul);
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Context.Emit(AddSubOp);
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Context.EmitStintzr(Op.Rd);
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}
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public static void Smulh(AILEmitterCtx Context)
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{
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AOpCodeMul Op = (AOpCodeMul)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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Context.EmitLdintzr(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SMulHi128));
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Context.EmitStintzr(Op.Rd);
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}
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public static void Umulh(AILEmitterCtx Context)
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{
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AOpCodeMul Op = (AOpCodeMul)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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Context.EmitLdintzr(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.UMulHi128));
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Context.EmitStintzr(Op.Rd);
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}
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}
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}
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