Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
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using ARMeilleure.Memory;
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using ARMeilleure.State;
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2018-12-18 06:33:36 +01:00
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using Ryujinx.HLE.HOS.Kernel.Common;
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using Ryujinx.HLE.HOS.Kernel.Process;
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using Ryujinx.HLE.HOS.Kernel.Threading;
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namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
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{
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partial class SvcHandler
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{
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public KernelResult CreateThread64(
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2020-01-13 03:04:28 +01:00
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[R(1)] ulong entrypoint,
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[R(2)] ulong argsPtr,
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[R(3)] ulong stackTop,
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[R(4)] int priority,
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[R(5)] int cpuCore,
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[R(1)] out int handle)
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2018-12-18 06:33:36 +01:00
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{
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return CreateThread(entrypoint, argsPtr, stackTop, priority, cpuCore, out handle);
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}
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private KernelResult CreateThread(
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ulong entrypoint,
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ulong argsPtr,
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ulong stackTop,
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int priority,
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int cpuCore,
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out int handle)
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{
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handle = 0;
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KProcess currentProcess = _system.Scheduler.GetCurrentProcess();
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if (cpuCore == -2)
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{
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cpuCore = currentProcess.DefaultCpuCore;
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}
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if ((uint)cpuCore >= KScheduler.CpuCoresCount || !currentProcess.IsCpuCoreAllowed(cpuCore))
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{
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return KernelResult.InvalidCpuCore;
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}
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if ((uint)priority >= KScheduler.PrioritiesCount || !currentProcess.IsPriorityAllowed(priority))
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{
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return KernelResult.InvalidPriority;
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}
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long timeout = KTimeManager.ConvertMillisecondsToNanoseconds(100);
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if (currentProcess.ResourceLimit != null &&
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!currentProcess.ResourceLimit.Reserve(LimitableResource.Thread, 1, timeout))
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{
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return KernelResult.ResLimitExceeded;
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}
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KThread thread = new KThread(_system);
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KernelResult result = currentProcess.InitializeThread(
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thread,
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entrypoint,
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argsPtr,
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stackTop,
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priority,
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cpuCore);
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2019-01-18 23:26:39 +01:00
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if (result == KernelResult.Success)
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2018-12-18 06:33:36 +01:00
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{
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2019-01-18 23:26:39 +01:00
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result = _process.HandleTable.GenerateHandle(thread, out handle);
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2018-12-18 06:33:36 +01:00
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}
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2019-01-18 23:26:39 +01:00
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else
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2018-12-18 06:33:36 +01:00
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{
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currentProcess.ResourceLimit?.Release(LimitableResource.Thread, 1);
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}
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2019-01-18 23:26:39 +01:00
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thread.DecrementReferenceCount();
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2018-12-18 06:33:36 +01:00
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return result;
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult StartThread64([R(0)] int handle)
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2018-12-18 06:33:36 +01:00
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{
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return StartThread(handle);
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}
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private KernelResult StartThread(int handle)
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{
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2019-01-18 23:26:39 +01:00
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KThread thread = _process.HandleTable.GetKThread(handle);
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2018-12-18 06:33:36 +01:00
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if (thread != null)
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{
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2019-01-18 23:26:39 +01:00
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thread.IncrementReferenceCount();
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KernelResult result = thread.Start();
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if (result == KernelResult.Success)
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{
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thread.IncrementReferenceCount();
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}
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thread.DecrementReferenceCount();
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return result;
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2018-12-18 06:33:36 +01:00
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}
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else
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{
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return KernelResult.InvalidHandle;
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}
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}
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public void ExitThread64()
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{
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ExitThread();
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}
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private void ExitThread()
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{
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KThread currentThread = _system.Scheduler.GetCurrentThread();
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_system.Scheduler.ExitThread(currentThread);
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currentThread.Exit();
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}
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2020-01-13 03:04:28 +01:00
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public void SleepThread64([R(0)] long timeout)
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2018-12-18 06:33:36 +01:00
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{
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SleepThread(timeout);
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}
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private void SleepThread(long timeout)
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{
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KThread currentThread = _system.Scheduler.GetCurrentThread();
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if (timeout < 1)
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{
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switch (timeout)
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{
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case 0: currentThread.Yield(); break;
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case -1: currentThread.YieldWithLoadBalancing(); break;
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case -2: currentThread.YieldAndWaitForLoadBalancing(); break;
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}
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}
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else
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{
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currentThread.Sleep(timeout);
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}
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult GetThreadPriority64([R(1)] int handle, [R(1)] out int priority)
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2018-12-18 06:33:36 +01:00
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{
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return GetThreadPriority(handle, out priority);
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}
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private KernelResult GetThreadPriority(int handle, out int priority)
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{
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KThread thread = _process.HandleTable.GetKThread(handle);
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if (thread != null)
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{
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priority = thread.DynamicPriority;
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return KernelResult.Success;
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}
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else
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{
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priority = 0;
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return KernelResult.InvalidHandle;
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}
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult SetThreadPriority64([R(0)] int handle, [R(1)] int priority)
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2018-12-18 06:33:36 +01:00
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{
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return SetThreadPriority(handle, priority);
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}
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public KernelResult SetThreadPriority(int handle, int priority)
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{
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2019-07-02 04:39:22 +02:00
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// TODO: NPDM check.
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2018-12-18 06:33:36 +01:00
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KThread thread = _process.HandleTable.GetKThread(handle);
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if (thread == null)
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{
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return KernelResult.InvalidHandle;
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}
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thread.SetPriority(priority);
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return KernelResult.Success;
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult GetThreadCoreMask64([R(2)] int handle, [R(1)] out int preferredCore, [R(2)] out long affinityMask)
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2018-12-18 06:33:36 +01:00
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{
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return GetThreadCoreMask(handle, out preferredCore, out affinityMask);
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}
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private KernelResult GetThreadCoreMask(int handle, out int preferredCore, out long affinityMask)
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{
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KThread thread = _process.HandleTable.GetKThread(handle);
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if (thread != null)
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{
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preferredCore = thread.PreferredCore;
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affinityMask = thread.AffinityMask;
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return KernelResult.Success;
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}
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else
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{
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preferredCore = 0;
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affinityMask = 0;
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return KernelResult.InvalidHandle;
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}
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult SetThreadCoreMask64([R(0)] int handle, [R(1)] int preferredCore, [R(2)] long affinityMask)
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2018-12-18 06:33:36 +01:00
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{
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return SetThreadCoreMask(handle, preferredCore, affinityMask);
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}
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private KernelResult SetThreadCoreMask(int handle, int preferredCore, long affinityMask)
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{
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KProcess currentProcess = _system.Scheduler.GetCurrentProcess();
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if (preferredCore == -2)
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{
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preferredCore = currentProcess.DefaultCpuCore;
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affinityMask = 1 << preferredCore;
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}
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else
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{
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if ((currentProcess.Capabilities.AllowedCpuCoresMask | affinityMask) !=
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currentProcess.Capabilities.AllowedCpuCoresMask)
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{
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return KernelResult.InvalidCpuCore;
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}
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if (affinityMask == 0)
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{
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return KernelResult.InvalidCombination;
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}
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if ((uint)preferredCore > 3)
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{
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if ((preferredCore | 2) != -1)
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{
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return KernelResult.InvalidCpuCore;
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}
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}
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else if ((affinityMask & (1 << preferredCore)) == 0)
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{
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return KernelResult.InvalidCombination;
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}
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}
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KThread thread = _process.HandleTable.GetKThread(handle);
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if (thread == null)
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{
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return KernelResult.InvalidHandle;
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}
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return thread.SetCoreAndAffinityMask(preferredCore, affinityMask);
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}
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public int GetCurrentProcessorNumber64()
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{
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return _system.Scheduler.GetCurrentThread().CurrentCore;
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult GetThreadId64([R(1)] int handle, [R(1)] out long threadUid)
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2018-12-18 06:33:36 +01:00
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{
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return GetThreadId(handle, out threadUid);
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}
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private KernelResult GetThreadId(int handle, out long threadUid)
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{
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KThread thread = _process.HandleTable.GetKThread(handle);
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if (thread != null)
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{
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threadUid = thread.ThreadUid;
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return KernelResult.Success;
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}
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else
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{
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threadUid = 0;
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return KernelResult.InvalidHandle;
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}
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult SetThreadActivity64([R(0)] int handle, [R(1)] bool pause)
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2018-12-18 06:33:36 +01:00
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{
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return SetThreadActivity(handle, pause);
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}
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private KernelResult SetThreadActivity(int handle, bool pause)
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{
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KThread thread = _process.HandleTable.GetObject<KThread>(handle);
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if (thread == null)
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{
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return KernelResult.InvalidHandle;
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}
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if (thread.Owner != _system.Scheduler.GetCurrentProcess())
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{
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return KernelResult.InvalidHandle;
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}
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if (thread == _system.Scheduler.GetCurrentThread())
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{
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return KernelResult.InvalidThread;
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}
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return thread.SetActivity(pause);
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}
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2020-01-13 03:04:28 +01:00
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public KernelResult GetThreadContext364([R(0)] ulong address, [R(1)] int handle)
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2018-12-18 06:33:36 +01:00
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{
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return GetThreadContext3(address, handle);
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}
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private KernelResult GetThreadContext3(ulong address, int handle)
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{
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KProcess currentProcess = _system.Scheduler.GetCurrentProcess();
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KThread currentThread = _system.Scheduler.GetCurrentThread();
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KThread thread = _process.HandleTable.GetObject<KThread>(handle);
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if (thread == null)
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{
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|
|
|
return KernelResult.InvalidHandle;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (thread.Owner != currentProcess)
|
|
|
|
{
|
|
|
|
return KernelResult.InvalidHandle;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (currentThread == thread)
|
|
|
|
{
|
|
|
|
return KernelResult.InvalidThread;
|
|
|
|
}
|
|
|
|
|
2019-10-31 19:09:03 +01:00
|
|
|
MemoryManager memory = currentProcess.CpuMemory;
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
|
|
|
|
|
|
memory.WriteUInt64((long)address + 0x0, thread.Context.GetX(0));
|
|
|
|
memory.WriteUInt64((long)address + 0x8, thread.Context.GetX(1));
|
|
|
|
memory.WriteUInt64((long)address + 0x10, thread.Context.GetX(2));
|
|
|
|
memory.WriteUInt64((long)address + 0x18, thread.Context.GetX(3));
|
|
|
|
memory.WriteUInt64((long)address + 0x20, thread.Context.GetX(4));
|
|
|
|
memory.WriteUInt64((long)address + 0x28, thread.Context.GetX(5));
|
|
|
|
memory.WriteUInt64((long)address + 0x30, thread.Context.GetX(6));
|
|
|
|
memory.WriteUInt64((long)address + 0x38, thread.Context.GetX(7));
|
|
|
|
memory.WriteUInt64((long)address + 0x40, thread.Context.GetX(8));
|
|
|
|
memory.WriteUInt64((long)address + 0x48, thread.Context.GetX(9));
|
|
|
|
memory.WriteUInt64((long)address + 0x50, thread.Context.GetX(10));
|
|
|
|
memory.WriteUInt64((long)address + 0x58, thread.Context.GetX(11));
|
|
|
|
memory.WriteUInt64((long)address + 0x60, thread.Context.GetX(12));
|
|
|
|
memory.WriteUInt64((long)address + 0x68, thread.Context.GetX(13));
|
|
|
|
memory.WriteUInt64((long)address + 0x70, thread.Context.GetX(14));
|
|
|
|
memory.WriteUInt64((long)address + 0x78, thread.Context.GetX(15));
|
|
|
|
memory.WriteUInt64((long)address + 0x80, thread.Context.GetX(16));
|
|
|
|
memory.WriteUInt64((long)address + 0x88, thread.Context.GetX(17));
|
|
|
|
memory.WriteUInt64((long)address + 0x90, thread.Context.GetX(18));
|
|
|
|
memory.WriteUInt64((long)address + 0x98, thread.Context.GetX(19));
|
|
|
|
memory.WriteUInt64((long)address + 0xa0, thread.Context.GetX(20));
|
|
|
|
memory.WriteUInt64((long)address + 0xa8, thread.Context.GetX(21));
|
|
|
|
memory.WriteUInt64((long)address + 0xb0, thread.Context.GetX(22));
|
|
|
|
memory.WriteUInt64((long)address + 0xb8, thread.Context.GetX(23));
|
|
|
|
memory.WriteUInt64((long)address + 0xc0, thread.Context.GetX(24));
|
|
|
|
memory.WriteUInt64((long)address + 0xc8, thread.Context.GetX(25));
|
|
|
|
memory.WriteUInt64((long)address + 0xd0, thread.Context.GetX(26));
|
|
|
|
memory.WriteUInt64((long)address + 0xd8, thread.Context.GetX(27));
|
|
|
|
memory.WriteUInt64((long)address + 0xe0, thread.Context.GetX(28));
|
|
|
|
memory.WriteUInt64((long)address + 0xe8, thread.Context.GetX(29));
|
|
|
|
memory.WriteUInt64((long)address + 0xf0, thread.Context.GetX(30));
|
|
|
|
memory.WriteUInt64((long)address + 0xf8, thread.Context.GetX(31));
|
2019-02-24 08:24:35 +01:00
|
|
|
|
|
|
|
memory.WriteInt64((long)address + 0x100, thread.LastPc);
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
|
|
memory.WriteUInt64((long)address + 0x108, (ulong)GetPsr(thread.Context));
|
|
|
|
|
|
|
|
memory.WriteVector128((long)address + 0x110, thread.Context.GetV(0));
|
|
|
|
memory.WriteVector128((long)address + 0x120, thread.Context.GetV(1));
|
|
|
|
memory.WriteVector128((long)address + 0x130, thread.Context.GetV(2));
|
|
|
|
memory.WriteVector128((long)address + 0x140, thread.Context.GetV(3));
|
|
|
|
memory.WriteVector128((long)address + 0x150, thread.Context.GetV(4));
|
|
|
|
memory.WriteVector128((long)address + 0x160, thread.Context.GetV(5));
|
|
|
|
memory.WriteVector128((long)address + 0x170, thread.Context.GetV(6));
|
|
|
|
memory.WriteVector128((long)address + 0x180, thread.Context.GetV(7));
|
|
|
|
memory.WriteVector128((long)address + 0x190, thread.Context.GetV(8));
|
|
|
|
memory.WriteVector128((long)address + 0x1a0, thread.Context.GetV(9));
|
|
|
|
memory.WriteVector128((long)address + 0x1b0, thread.Context.GetV(10));
|
|
|
|
memory.WriteVector128((long)address + 0x1c0, thread.Context.GetV(11));
|
|
|
|
memory.WriteVector128((long)address + 0x1d0, thread.Context.GetV(12));
|
|
|
|
memory.WriteVector128((long)address + 0x1e0, thread.Context.GetV(13));
|
|
|
|
memory.WriteVector128((long)address + 0x1f0, thread.Context.GetV(14));
|
|
|
|
memory.WriteVector128((long)address + 0x200, thread.Context.GetV(15));
|
|
|
|
memory.WriteVector128((long)address + 0x210, thread.Context.GetV(16));
|
|
|
|
memory.WriteVector128((long)address + 0x220, thread.Context.GetV(17));
|
|
|
|
memory.WriteVector128((long)address + 0x230, thread.Context.GetV(18));
|
|
|
|
memory.WriteVector128((long)address + 0x240, thread.Context.GetV(19));
|
|
|
|
memory.WriteVector128((long)address + 0x250, thread.Context.GetV(20));
|
|
|
|
memory.WriteVector128((long)address + 0x260, thread.Context.GetV(21));
|
|
|
|
memory.WriteVector128((long)address + 0x270, thread.Context.GetV(22));
|
|
|
|
memory.WriteVector128((long)address + 0x280, thread.Context.GetV(23));
|
|
|
|
memory.WriteVector128((long)address + 0x290, thread.Context.GetV(24));
|
|
|
|
memory.WriteVector128((long)address + 0x2a0, thread.Context.GetV(25));
|
|
|
|
memory.WriteVector128((long)address + 0x2b0, thread.Context.GetV(26));
|
|
|
|
memory.WriteVector128((long)address + 0x2c0, thread.Context.GetV(27));
|
|
|
|
memory.WriteVector128((long)address + 0x2d0, thread.Context.GetV(28));
|
|
|
|
memory.WriteVector128((long)address + 0x2e0, thread.Context.GetV(29));
|
|
|
|
memory.WriteVector128((long)address + 0x2f0, thread.Context.GetV(30));
|
|
|
|
memory.WriteVector128((long)address + 0x300, thread.Context.GetV(31));
|
|
|
|
|
|
|
|
memory.WriteInt32((long)address + 0x310, (int)thread.Context.Fpcr);
|
|
|
|
memory.WriteInt32((long)address + 0x314, (int)thread.Context.Fpsr);
|
|
|
|
memory.WriteInt64((long)address + 0x318, thread.Context.Tpidr);
|
2018-12-18 06:33:36 +01:00
|
|
|
|
|
|
|
return KernelResult.Success;
|
|
|
|
}
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
|
|
|
2019-10-31 19:09:03 +01:00
|
|
|
private static int GetPsr(ExecutionContext context)
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
|
|
{
|
|
|
|
return (context.GetPstateFlag(PState.NFlag) ? (1 << 31) : 0) |
|
|
|
|
(context.GetPstateFlag(PState.ZFlag) ? (1 << 30) : 0) |
|
|
|
|
(context.GetPstateFlag(PState.CFlag) ? (1 << 29) : 0) |
|
|
|
|
(context.GetPstateFlag(PState.VFlag) ? (1 << 28) : 0);
|
|
|
|
}
|
2018-12-18 06:33:36 +01:00
|
|
|
}
|
|
|
|
}
|