mirror of
https://github.com/GreemDev/Ryujinx
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117 lines
4 KiB
C#
117 lines
4 KiB
C#
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#define SimdShImm32
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using ARMeilleure.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdShImm32")]
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public sealed class CpuTestSimdShImm32 : CpuTest32
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{
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#if SimdShImm32
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private const int RndCnt = 2;
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[Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, #<imm>")]
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public void Vshl_Imm([Values(0u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u, 3u)] uint size,
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[Random(RndCnt), Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool q)
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{
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uint opcode = 0xf2800510u; // VORR.I32 D0, #0 (immediate value changes it into SHL)
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if (q)
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{
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opcode |= 1 << 6;
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rm <<= 1;
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rd <<= 1;
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}
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uint imm = 1u << ((int)size + 3);
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imm |= shiftImm & (imm - 1);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((imm & 0x3f) << 16) | ((imm & 0x40) << 1);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSHR.<size> {<Vd>}, <Vm>, #<imm>")]
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public void Vshr_Imm([Values(0u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u, 3u)] uint size,
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[Random(RndCnt), Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool u,
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[Values] bool q)
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{
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uint opcode = 0xf2800010u; // VMOV.I32 D0, #0 (immediate value changes it into SHR)
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if (q)
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{
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opcode |= 1 << 6;
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rm <<= 1;
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rd <<= 1;
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}
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if (u)
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{
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opcode |= 1 << 24;
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}
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uint imm = 1u << ((int)size + 3);
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imm |= shiftImm & (imm - 1);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((imm & 0x3f) << 16) | ((imm & 0x40) << 1);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSHRN.<size> {<Vd>}, <Vm>, #<imm>")]
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public void Vshrn_Imm([Values(0u, 1u)] uint rd,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt), Values(0u)] uint shiftImm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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{
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uint opcode = 0xf2800810u; // VMOV.I16 D0, #0 (immediate value changes it into SHRN)
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uint imm = 1u << ((int)size + 3);
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imm |= shiftImm & (imm - 1);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((imm & 0x3f) << 16);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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