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Fix CPU FCVTN instruction implementation (slow path) (#4159)

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* Fix CPU FCVTN instruction implementation (slow path)

* PPTC version bump
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gdkchan 2022-12-21 20:05:58 -03:00 committed by GitHub
parent 1cca3e99ab
commit 219f63ff4e
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GPG key ID: 4AEE18F83AFDEB23
3 changed files with 6 additions and 8 deletions
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4
ARMeilleure/Instructions/InstEmitSimdCvt.cs
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@ -381,7 +381,7 @@ namespace ARMeilleure.Instructions
for (int index = 0; index < elems; index++)
{
Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
if (sizeF == 0)
{
@ -389,8 +389,6 @@ namespace ARMeilleure.Instructions
Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
context.LoadFromContext();
e = context.ZeroExtend16(OperandType.I64, e);
res = EmitVectorInsert(context, res, e, part + index, 1);
}
else /* if (sizeF == 1) */

2
ARMeilleure/Translation/PTC/Ptc.cs
View file

@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
private const string OuterHeaderMagicString = "PTCohd\0\0";
private const string InnerHeaderMagicString = "PTCihd\0\0";
private const uint InternalVersion = 4140; //! To be incremented manually for each change to the ARMeilleure project.
private const uint InternalVersion = 4159; //! To be incremented manually for each change to the ARMeilleure project.
private const string ActualDir = "0";
private const string BackupDir = "1";

8
Ryujinx.Tests/Cpu/CpuTestSimd.cs
View file

@ -2176,8 +2176,8 @@ namespace Ryujinx.Tests.Cpu
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= ((q & 1) << 30);
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, a);
V128 v0 = MakeVectorE0E1(z, a);
V128 v1 = MakeVectorE0E1(a, z);
int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
@ -2202,8 +2202,8 @@ namespace Ryujinx.Tests.Cpu
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= ((q & 1) << 30);
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, a);
V128 v0 = MakeVectorE0E1(z, a);
V128 v1 = MakeVectorE0E1(a, z);
SingleOpcode(opcodes, v0: v0, v1: v1);