mirror of
https://github.com/GreemDev/Ryujinx
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PPTC Profiles & FunctionTable options
The Sparse Jit Function Table sizes now depend on the LowPowerPTC setting. This means lower power devices won't be impacted as hard by the higher ram speed requirement of GiantBlock. Also added functionality to the PPTC Initializer so it now supports different PPTC Profiles simultaneously, which makes switching between TinyBlock/LowPower and GiantBlock/HighPower seamless. This also opens the door for the potential of PPTC cache with exefs mods enabled in the future. Default (aka HighPower) currently has an Avalonia bug that causes a crash when starting a game, it can be bypassed be clicking the window multiple times durring loading until the window unfreezes.
This commit is contained in:
parent
3f6d42a449
commit
b9c20e551a
23 changed files with 79 additions and 42 deletions
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@ -36,11 +36,32 @@ namespace ARMeilleure.Common
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new( 1, 9),
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};
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public static AddressTableLevel[] GetArmPreset(bool for64Bits, bool sparse)
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private static readonly AddressTableLevel[] _levels64BitSparseGiant =
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new AddressTableLevel[]
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{
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new( 38, 1),
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new( 2, 36),
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};
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private static readonly AddressTableLevel[] _levels32BitSparseGiant =
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new AddressTableLevel[]
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{
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new( 31, 1),
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new( 1, 30),
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};
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public static AddressTableLevel[] GetArmPreset(bool for64Bits, bool sparse, bool lowPower = false)
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{
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if (sparse)
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{
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if (lowPower)
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{
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return for64Bits ? _levels64BitSparseTiny : _levels32BitSparseTiny;
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}
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else
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{
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return for64Bits ? _levels64BitSparseGiant : _levels32BitSparseGiant;
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}
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}
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else
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{
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@ -30,7 +30,7 @@ namespace ARMeilleure.Translation.PTC
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const uint InternalVersion = 6986; //! To be incremented manually for each change to the ARMeilleure project.
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private const uint InternalVersion = 6991; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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@ -102,7 +102,7 @@ namespace ARMeilleure.Translation.PTC
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Disable();
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}
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public void Initialize(string titleIdText, string displayVersion, bool enabled, MemoryManagerType memoryMode)
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public void Initialize(string titleIdText, string displayVersion, bool enabled, MemoryManagerType memoryMode, string cacheSelector)
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{
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Wait();
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@ -141,8 +141,8 @@ namespace ARMeilleure.Translation.PTC
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Directory.CreateDirectory(workPathBackup);
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}
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CachePathActual = Path.Combine(workPathActual, DisplayVersion);
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CachePathBackup = Path.Combine(workPathBackup, DisplayVersion);
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CachePathActual = Path.Combine(workPathActual, DisplayVersion) + "-" + cacheSelector;
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CachePathBackup = Path.Combine(workPathBackup, DisplayVersion) + "-" + cacheSelector;
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PreLoad();
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Profiler.PreLoad();
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@ -58,9 +58,9 @@ namespace ARMeilleure.Translation
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FunctionTable.Fill = (ulong)Stubs.SlowDispatchStub;
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}
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public IPtcLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled)
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public IPtcLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled, string cacheSelector)
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{
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_ptc.Initialize(titleIdText, displayVersion, enabled, Memory.Type);
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_ptc.Initialize(titleIdText, displayVersion, enabled, Memory.Type, cacheSelector);
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return _ptc;
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}
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@ -178,12 +178,12 @@ namespace ARMeilleure.Common
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/// <param name="for64Bits">True if the guest is A64, false otherwise</param>
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/// <param name="type">Memory manager type</param>
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/// <returns>An <see cref="AddressTable{TEntry}"/> for ARM function lookup</returns>
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public static AddressTable<TEntry> CreateForArm(bool for64Bits, MemoryManagerType type)
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public static AddressTable<TEntry> CreateForArm(bool for64Bits, MemoryManagerType type, bool lowPower)
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{
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// Assume software memory means that we don't want to use any signal handlers.
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bool sparse = type != MemoryManagerType.SoftwareMmu && type != MemoryManagerType.SoftwarePageTable;
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return new AddressTable<TEntry>(AddressTablePresets.GetArmPreset(for64Bits, sparse), sparse);
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return new AddressTable<TEntry>(AddressTablePresets.GetArmPreset(for64Bits, sparse, lowPower), sparse);
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}
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/// <summary>
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@ -9,7 +9,7 @@ namespace Ryujinx.Cpu.AppleHv
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private readonly ITickSource _tickSource;
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private readonly HvMemoryManager _memoryManager;
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public HvCpuContext(ITickSource tickSource, IMemoryManager memory, bool for64Bit)
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public HvCpuContext(ITickSource tickSource, IMemoryManager memory, bool for64Bit, bool lowPower)
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{
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_tickSource = tickSource;
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_memoryManager = (HvMemoryManager)memory;
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@ -32,7 +32,7 @@ namespace Ryujinx.Cpu.AppleHv
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{
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}
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public IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled)
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public IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled, string cacheSelector)
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{
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return new DummyDiskCacheLoadState();
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}
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@ -14,9 +14,9 @@ namespace Ryujinx.Cpu.AppleHv
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}
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/// <inheritdoc/>
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public ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit)
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public ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit, bool lowPower)
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{
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return new HvCpuContext(_tickSource, memoryManager, for64Bit);
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return new HvCpuContext(_tickSource, memoryManager, for64Bit, lowPower);
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}
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}
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}
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@ -48,7 +48,7 @@ namespace Ryujinx.Cpu
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/// <param name="displayVersion">Version of the application</param>
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/// <param name="enabled">True if the cache should be loaded from disk if it exists, false otherwise</param>
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/// <returns>Disk cache load progress reporter and manager</returns>
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IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled);
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IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled, string cacheSelector);
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/// <summary>
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/// Indicates that code has been loaded into guest memory, and that it might be executed in the future.
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@ -13,6 +13,6 @@ namespace Ryujinx.Cpu
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/// <param name="memoryManager">Memory manager for the address space of the context</param>
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/// <param name="for64Bit">Indicates if the context will be used to run 64-bit or 32-bit Arm code</param>
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/// <returns>CPU context</returns>
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ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit);
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ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit, bool lowPower);
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}
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}
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@ -12,10 +12,10 @@ namespace Ryujinx.Cpu.Jit
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private readonly Translator _translator;
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private readonly AddressTable<ulong> _functionTable;
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public JitCpuContext(ITickSource tickSource, IMemoryManager memory, bool for64Bit)
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public JitCpuContext(ITickSource tickSource, IMemoryManager memory, bool for64Bit, bool lowPower)
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{
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_tickSource = tickSource;
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_functionTable = AddressTable<ulong>.CreateForArm(for64Bit, memory.Type);
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_functionTable = AddressTable<ulong>.CreateForArm(for64Bit, memory.Type, lowPower);
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_translator = new Translator(new JitMemoryAllocator(forJit: true), memory, _functionTable);
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if (memory.Type.IsHostMappedOrTracked())
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@ -50,9 +50,9 @@ namespace Ryujinx.Cpu.Jit
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}
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/// <inheritdoc/>
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public IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled)
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public IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled, string cacheSelector)
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{
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return new JitDiskCacheLoadState(_translator.LoadDiskCache(titleIdText, displayVersion, enabled));
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return new JitDiskCacheLoadState(_translator.LoadDiskCache(titleIdText, displayVersion, enabled, cacheSelector));
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}
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/// <inheritdoc/>
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@ -12,9 +12,9 @@ namespace Ryujinx.Cpu.Jit
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}
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/// <inheritdoc/>
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public ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit)
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public ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit, bool lowPower)
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{
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return new JitCpuContext(_tickSource, memoryManager, for64Bit);
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return new JitCpuContext(_tickSource, memoryManager, for64Bit, lowPower);
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}
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}
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}
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@ -11,11 +11,11 @@ namespace Ryujinx.Cpu.LightningJit
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private readonly Translator _translator;
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private readonly AddressTable<ulong> _functionTable;
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public LightningJitCpuContext(ITickSource tickSource, IMemoryManager memory, bool for64Bit)
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public LightningJitCpuContext(ITickSource tickSource, IMemoryManager memory, bool for64Bit, bool lowPower)
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{
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_tickSource = tickSource;
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_functionTable = AddressTable<ulong>.CreateForArm(for64Bit, memory.Type);
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_functionTable = AddressTable<ulong>.CreateForArm(for64Bit, memory.Type, lowPower);
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_translator = new Translator(memory, _functionTable);
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@ -46,7 +46,7 @@ namespace Ryujinx.Cpu.LightningJit
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}
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/// <inheritdoc/>
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public IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled)
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public IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled, string cacheSelector)
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{
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return new DummyDiskCacheLoadState();
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}
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@ -12,9 +12,9 @@ namespace Ryujinx.Cpu.LightningJit
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}
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/// <inheritdoc/>
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public ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit)
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public ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit, bool lowPower)
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{
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return new LightningJitCpuContext(_tickSource, memoryManager, for64Bit);
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return new LightningJitCpuContext(_tickSource, memoryManager, for64Bit, lowPower);
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}
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}
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}
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@ -98,6 +98,11 @@ namespace Ryujinx.HLE
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/// </summary>
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internal readonly bool EnablePtc;
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/// <summary>
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/// Control if the Profiled Translation Cache (PTC) should run in low power mode.
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/// </summary>
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internal readonly bool LowPowerPtc;
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/// <summary>
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/// Control if the guest application should be told that there is a Internet connection available.
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/// </summary>
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@ -198,6 +203,7 @@ namespace Ryujinx.HLE
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bool enableVsync,
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bool enableDockedMode,
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bool enablePtc,
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bool lowPowerPtc,
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bool enableInternetAccess,
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IntegrityCheckLevel fsIntegrityCheckLevel,
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int fsGlobalAccessLogMode,
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EnableVsync = enableVsync;
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EnableDockedMode = enableDockedMode;
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EnablePtc = enablePtc;
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LowPowerPtc = lowPowerPtc;
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EnableInternetAccess = enableInternetAccess;
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FsIntegrityCheckLevel = fsIntegrityCheckLevel;
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FsGlobalAccessLogMode = fsGlobalAccessLogMode;
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@ -13,7 +13,8 @@ namespace Ryujinx.HLE.HOS
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string displayVersion,
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bool diskCacheEnabled,
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ulong codeAddress,
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ulong codeSize);
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ulong codeSize,
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string cacheSelector);
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}
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class ArmProcessContext<T> : IArmProcessContext where T : class, IVirtualMemoryManagerTracked, IMemoryManager
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@ -33,7 +34,8 @@ namespace Ryujinx.HLE.HOS
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GpuContext gpuContext,
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T memoryManager,
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ulong addressSpaceSize,
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bool for64Bit)
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bool for64Bit,
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bool lowPower)
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{
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if (memoryManager is IRefCounted rc)
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{
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@ -44,7 +46,7 @@ namespace Ryujinx.HLE.HOS
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_pid = pid;
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_gpuContext = gpuContext;
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_cpuContext = cpuEngine.CreateCpuContext(memoryManager, for64Bit);
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_cpuContext = cpuEngine.CreateCpuContext(memoryManager, for64Bit, lowPower);
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_memoryManager = memoryManager;
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AddressSpaceSize = addressSpaceSize;
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@ -67,10 +69,11 @@ namespace Ryujinx.HLE.HOS
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string displayVersion,
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bool diskCacheEnabled,
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ulong codeAddress,
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ulong codeSize)
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ulong codeSize,
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string cacheSelector)
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{
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_cpuContext.PrepareCodeRange(codeAddress, codeSize);
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return _cpuContext.LoadDiskCache(titleIdText, displayVersion, diskCacheEnabled);
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return _cpuContext.LoadDiskCache(titleIdText, displayVersion, diskCacheEnabled, cacheSelector);
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}
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public void InvalidateCacheRegion(ulong address, ulong size)
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@ -48,12 +48,13 @@ namespace Ryujinx.HLE.HOS
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IArmProcessContext processContext;
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bool isArm64Host = RuntimeInformation.ProcessArchitecture == Architecture.Arm64;
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bool isLowPower = context.Device.Configuration.LowPowerPtc;
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if (OperatingSystem.IsMacOS() && isArm64Host && for64Bit && context.Device.Configuration.UseHypervisor)
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{
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var cpuEngine = new HvEngine(_tickSource);
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var memoryManager = new HvMemoryManager(context.Memory, addressSpaceSize, invalidAccessHandler);
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processContext = new ArmProcessContext<HvMemoryManager>(pid, cpuEngine, _gpu, memoryManager, addressSpaceSize, for64Bit);
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processContext = new ArmProcessContext<HvMemoryManager>(pid, cpuEngine, _gpu, memoryManager, addressSpaceSize, for64Bit, isLowPower);
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}
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else
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{
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@ -87,7 +88,7 @@ namespace Ryujinx.HLE.HOS
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{
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case MemoryManagerMode.SoftwarePageTable:
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var memoryManager = new MemoryManager(context.Memory, addressSpaceSize, invalidAccessHandler);
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processContext = new ArmProcessContext<MemoryManager>(pid, cpuEngine, _gpu, memoryManager, addressSpaceSize, for64Bit);
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processContext = new ArmProcessContext<MemoryManager>(pid, cpuEngine, _gpu, memoryManager, addressSpaceSize, for64Bit, isLowPower);
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break;
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case MemoryManagerMode.HostMapped:
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@ -95,7 +96,7 @@ namespace Ryujinx.HLE.HOS
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if (addressSpace == null)
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{
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var memoryManagerHostTracked = new MemoryManagerHostTracked(context.Memory, addressSpaceSize, mode == MemoryManagerMode.HostMappedUnsafe, invalidAccessHandler);
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processContext = new ArmProcessContext<MemoryManagerHostTracked>(pid, cpuEngine, _gpu, memoryManagerHostTracked, addressSpaceSize, for64Bit);
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processContext = new ArmProcessContext<MemoryManagerHostTracked>(pid, cpuEngine, _gpu, memoryManagerHostTracked, addressSpaceSize, for64Bit, isLowPower);
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}
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else
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{
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@ -105,7 +106,7 @@ namespace Ryujinx.HLE.HOS
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}
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var memoryManagerHostMapped = new MemoryManagerHostMapped(addressSpace, mode == MemoryManagerMode.HostMappedUnsafe, invalidAccessHandler);
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processContext = new ArmProcessContext<MemoryManagerHostMapped>(pid, cpuEngine, _gpu, memoryManagerHostMapped, addressSpace.AddressSpaceSize, for64Bit);
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processContext = new ArmProcessContext<MemoryManagerHostMapped>(pid, cpuEngine, _gpu, memoryManagerHostMapped, addressSpace.AddressSpaceSize, for64Bit, isLowPower);
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}
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break;
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@ -114,7 +115,7 @@ namespace Ryujinx.HLE.HOS
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}
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}
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DiskCacheLoadState = processContext.Initialize(_titleIdText, _displayVersion, _diskCacheEnabled, _codeAddress, _codeSize);
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DiskCacheLoadState = processContext.Initialize(_titleIdText, _displayVersion, _diskCacheEnabled, _codeAddress, _codeSize, isLowPower ? "LowPower" : "HighPower");
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return processContext;
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}
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@ -106,6 +106,9 @@ namespace Ryujinx.Headless.SDL2
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[Option("disable-ptc", Required = false, HelpText = "Disables profiled persistent translation cache.")]
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public bool DisablePTC { get; set; }
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[Option("low-power-ptc", Required = false, HelpText = "Increases PTC performance for low power systems.")]
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public bool LowPowerPTC { get; set; }
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[Option("enable-internet-connection", Required = false, Default = false, HelpText = "Enables guest Internet connection.")]
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public bool EnableInternetAccess { get; set; }
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@ -566,6 +566,7 @@ namespace Ryujinx.Headless.SDL2
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!options.DisableVSync,
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!options.DisableDockedMode,
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!options.DisablePTC,
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options.LowPowerPTC,
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options.EnableInternetAccess,
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!options.DisableFsIntegrityChecks ? IntegrityCheckLevel.ErrorOnInvalid : IntegrityCheckLevel.None,
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options.FsGlobalAccessLogMode,
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@ -11,9 +11,9 @@ namespace Ryujinx.Tests.Cpu
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{
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private readonly Translator _translator;
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public CpuContext(IMemoryManager memory, bool for64Bit)
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public CpuContext(IMemoryManager memory, bool for64Bit, bool lowPower)
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{
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_translator = new Translator(new JitMemoryAllocator(), memory, AddressTable<ulong>.CreateForArm(for64Bit, memory.Type));
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_translator = new Translator(new JitMemoryAllocator(), memory, AddressTable<ulong>.CreateForArm(for64Bit, memory.Type, lowPower));
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memory.UnmapEvent += UnmapHandler;
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}
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@ -62,7 +62,7 @@ namespace Ryujinx.Tests.Cpu
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_context = CpuContext.CreateExecutionContext();
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_cpuContext = new CpuContext(_memory, for64Bit: true);
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_cpuContext = new CpuContext(_memory, for64Bit: true, lowPower: false);
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// Prevent registering LCQ functions in the FunctionTable to avoid initializing and populating the table,
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// which improves test durations.
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@ -57,7 +57,7 @@ namespace Ryujinx.Tests.Cpu
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_context = CpuContext.CreateExecutionContext();
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_context.IsAarch32 = true;
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_cpuContext = new CpuContext(_memory, for64Bit: false);
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_cpuContext = new CpuContext(_memory, for64Bit: false, lowPower: false);
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// Prevent registering LCQ functions in the FunctionTable to avoid initializing and populating the table,
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// which improves test durations.
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@ -22,7 +22,7 @@ namespace Ryujinx.Tests.Cpu
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_translator ??= new Translator(
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new JitMemoryAllocator(),
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new MockMemoryManager(),
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AddressTable<ulong>.CreateForArm(true, MemoryManagerType.SoftwarePageTable));
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AddressTable<ulong>.CreateForArm(true, MemoryManagerType.SoftwarePageTable, lowPower: false));
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}
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[MethodImpl(MethodImplOptions.NoInlining | MethodImplOptions.NoOptimization)]
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@ -58,7 +58,7 @@ namespace Ryujinx.Tests.Memory
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_translator ??= new Translator(
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new JitMemoryAllocator(),
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new MockMemoryManager(),
|
||||
AddressTable<ulong>.CreateForArm(true, MemoryManagerType.SoftwarePageTable));
|
||||
AddressTable<ulong>.CreateForArm(true, MemoryManagerType.SoftwarePageTable, lowPower: false));
|
||||
}
|
||||
|
||||
[Test]
|
||||
|
|
|
@ -871,6 +871,7 @@ namespace Ryujinx.Ava
|
|||
ConfigurationState.Instance.Graphics.EnableVsync,
|
||||
ConfigurationState.Instance.System.EnableDockedMode,
|
||||
ConfigurationState.Instance.System.EnablePtc,
|
||||
ConfigurationState.Instance.System.EnableLowPowerPtc,
|
||||
ConfigurationState.Instance.System.EnableInternetAccess,
|
||||
ConfigurationState.Instance.System.EnableFsIntegrityChecks ? IntegrityCheckLevel.ErrorOnInvalid : IntegrityCheckLevel.None,
|
||||
ConfigurationState.Instance.System.FsGlobalAccessLogMode,
|
||||
|
|
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Reference in a new issue