mirror of
https://github.com/GreemDev/Ryujinx
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45ce540b9b
* ARMeilleure: Add `GFNI` detection This is intended for utilizing the `gf2p8affineqb` instruction * ARMeilleure: Add `gf2p8affineqb` Not using the VEX or EVEX-form of this instruction is intentional. There are `GFNI`-chips that do not support AVX(so no VEX encoding) such as Tremont(Lakefield) chips as well as Jasper Lake.13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)* ARMeilleure: Add `gfni` acceleration of `Rbit_V` Passes all `Rbit_V*` unit tests on my `i9-11900k` * ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V` Also added a fast-path for when the shift amount is greater than the size of the element. * ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V` * ARMeilleure: Increment InternalVersion * ARMeilleure: Fix Intrinsic and Assembler Table alignment `gf2p8affineqb` is the longest instruction name I know of. It shouldn't get any wider than this. * ARMeilleure: Remove SSE2+SHA requirement for GFNI * ARMeilleure Add `X86GetGf2p8LogicalShiftLeft` Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction. * ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
48 lines
No EOL
3 KiB
C#
48 lines
No EOL
3 KiB
C#
using ARMeilleure.CodeGen.X86;
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namespace ARMeilleure
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{
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public static class Optimizations
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{
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public static bool FastFP { get; set; } = true;
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public static bool AllowLcqInFunctionTable { get; set; } = true;
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public static bool UseUnmanagedDispatchLoop { get; set; } = true;
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public static bool UseSseIfAvailable { get; set; } = true;
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public static bool UseSse2IfAvailable { get; set; } = true;
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public static bool UseSse3IfAvailable { get; set; } = true;
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public static bool UseSsse3IfAvailable { get; set; } = true;
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public static bool UseSse41IfAvailable { get; set; } = true;
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public static bool UseSse42IfAvailable { get; set; } = true;
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public static bool UsePopCntIfAvailable { get; set; } = true;
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public static bool UseAvxIfAvailable { get; set; } = true;
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public static bool UseF16cIfAvailable { get; set; } = true;
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public static bool UseFmaIfAvailable { get; set; } = true;
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public static bool UseAesniIfAvailable { get; set; } = true;
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public static bool UsePclmulqdqIfAvailable { get; set; } = true;
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public static bool UseShaIfAvailable { get; set; } = true;
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public static bool UseGfniIfAvailable { get; set; } = true;
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public static bool ForceLegacySse
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{
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get => HardwareCapabilities.ForceLegacySse;
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set => HardwareCapabilities.ForceLegacySse = value;
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}
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internal static bool UseSse => UseSseIfAvailable && HardwareCapabilities.SupportsSse;
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internal static bool UseSse2 => UseSse2IfAvailable && HardwareCapabilities.SupportsSse2;
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internal static bool UseSse3 => UseSse3IfAvailable && HardwareCapabilities.SupportsSse3;
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internal static bool UseSsse3 => UseSsse3IfAvailable && HardwareCapabilities.SupportsSsse3;
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internal static bool UseSse41 => UseSse41IfAvailable && HardwareCapabilities.SupportsSse41;
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internal static bool UseSse42 => UseSse42IfAvailable && HardwareCapabilities.SupportsSse42;
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internal static bool UsePopCnt => UsePopCntIfAvailable && HardwareCapabilities.SupportsPopcnt;
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internal static bool UseAvx => UseAvxIfAvailable && HardwareCapabilities.SupportsAvx && !ForceLegacySse;
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internal static bool UseF16c => UseF16cIfAvailable && HardwareCapabilities.SupportsF16c;
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internal static bool UseFma => UseFmaIfAvailable && HardwareCapabilities.SupportsFma;
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internal static bool UseAesni => UseAesniIfAvailable && HardwareCapabilities.SupportsAesni;
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internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && HardwareCapabilities.SupportsPclmulqdq;
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internal static bool UseSha => UseShaIfAvailable && HardwareCapabilities.SupportsSha;
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internal static bool UseGfni => UseGfniIfAvailable && HardwareCapabilities.SupportsGfni;
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}
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} |