mirror of
https://github.com/GreemDev/Ryujinx
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* ARMeilleure: Add `GFNI` detection This is intended for utilizing the `gf2p8affineqb` instruction * ARMeilleure: Add `gf2p8affineqb` Not using the VEX or EVEX-form of this instruction is intentional. There are `GFNI`-chips that do not support AVX(so no VEX encoding) such as Tremont(Lakefield) chips as well as Jasper Lake.13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)* ARMeilleure: Add `gfni` acceleration of `Rbit_V` Passes all `Rbit_V*` unit tests on my `i9-11900k` * ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V` Also added a fast-path for when the shift amount is greater than the size of the element. * ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V` * ARMeilleure: Increment InternalVersion * ARMeilleure: Fix Intrinsic and Assembler Table alignment `gf2p8affineqb` is the longest instruction name I know of. It shouldn't get any wider than this. * ARMeilleure: Remove SSE2+SHA requirement for GFNI * ARMeilleure Add `X86GetGf2p8LogicalShiftLeft` Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction. * ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
89 lines
No EOL
3.2 KiB
C#
89 lines
No EOL
3.2 KiB
C#
using System;
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using System.Runtime.Intrinsics.X86;
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namespace ARMeilleure.CodeGen.X86
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{
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static class HardwareCapabilities
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{
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static HardwareCapabilities()
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{
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if (!X86Base.IsSupported)
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{
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return;
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}
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(int maxNum, _, _, _) = X86Base.CpuId(0x00000000, 0x00000000);
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(_, _, int ecx1, int edx1) = X86Base.CpuId(0x00000001, 0x00000000);
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FeatureInfo1Edx = (FeatureFlags1Edx)edx1;
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FeatureInfo1Ecx = (FeatureFlags1Ecx)ecx1;
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if (maxNum >= 7)
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{
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(_, int ebx7, int ecx7, _) = X86Base.CpuId(0x00000007, 0x00000000);
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FeatureInfo7Ebx = (FeatureFlags7Ebx)ebx7;
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FeatureInfo7Ecx = (FeatureFlags7Ecx)ecx7;
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}
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}
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[Flags]
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public enum FeatureFlags1Edx
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{
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Sse = 1 << 25,
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Sse2 = 1 << 26
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}
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[Flags]
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public enum FeatureFlags1Ecx
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{
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Sse3 = 1 << 0,
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Pclmulqdq = 1 << 1,
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Ssse3 = 1 << 9,
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Fma = 1 << 12,
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Sse41 = 1 << 19,
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Sse42 = 1 << 20,
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Popcnt = 1 << 23,
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Aes = 1 << 25,
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Avx = 1 << 28,
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F16c = 1 << 29
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}
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[Flags]
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public enum FeatureFlags7Ebx
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{
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Avx2 = 1 << 5,
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Sha = 1 << 29
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}
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[Flags]
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public enum FeatureFlags7Ecx
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{
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Gfni = 1 << 8,
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}
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public static FeatureFlags1Edx FeatureInfo1Edx { get; }
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public static FeatureFlags1Ecx FeatureInfo1Ecx { get; }
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public static FeatureFlags7Ebx FeatureInfo7Ebx { get; } = 0;
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public static FeatureFlags7Ecx FeatureInfo7Ecx { get; } = 0;
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public static bool SupportsSse => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse);
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public static bool SupportsSse2 => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse2);
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public static bool SupportsSse3 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Sse3);
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public static bool SupportsPclmulqdq => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Pclmulqdq);
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public static bool SupportsSsse3 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Ssse3);
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public static bool SupportsFma => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Fma);
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public static bool SupportsSse41 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Sse41);
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public static bool SupportsSse42 => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Sse42);
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public static bool SupportsPopcnt => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Popcnt);
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public static bool SupportsAesni => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Aes);
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public static bool SupportsAvx => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.Avx);
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public static bool SupportsAvx2 => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx2) && SupportsAvx;
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public static bool SupportsF16c => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.F16c);
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public static bool SupportsSha => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Sha);
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public static bool SupportsGfni => FeatureInfo7Ecx.HasFlag(FeatureFlags7Ecx.Gfni);
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public static bool ForceLegacySse { get; set; }
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public static bool SupportsVexEncoding => SupportsAvx && !ForceLegacySse;
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}
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} |