mirror of
https://github.com/GreemDev/Ryujinx
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97 lines
No EOL
2.3 KiB
C#
97 lines
No EOL
2.3 KiB
C#
using ChocolArm64.Instruction;
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using ChocolArm64.State;
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namespace ChocolArm64.Decoder
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{
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class AOpCodeSimdMemSs : AOpCodeMemReg, IAOpCodeSimd
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{
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public int SElems { get; private set; }
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public int Index { get; private set; }
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public bool Replicate { get; private set; }
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public bool WBack { get; private set; }
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public AOpCodeSimdMemSs(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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{
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int Size = (OpCode >> 10) & 3;
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int S = (OpCode >> 12) & 1;
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int SElems = (OpCode >> 12) & 2;
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int Scale = (OpCode >> 14) & 3;
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int L = (OpCode >> 22) & 1;
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int Q = (OpCode >> 30) & 1;
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SElems |= (OpCode >> 21) & 1;
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SElems++;
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int Index = (Q << 3) | (S << 2) | Size;
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switch (Scale)
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{
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case 1:
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{
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if ((Size & 1) != 0)
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{
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Inst = AInst.Undefined;
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return;
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}
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Index >>= 1;
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break;
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}
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case 2:
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{
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if ((Size & 2) != 0 ||
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((Size & 1) != 0 && S != 0))
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{
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Inst = AInst.Undefined;
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return;
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}
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if ((Size & 1) != 0)
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{
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Index >>= 3;
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Scale = 3;
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}
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else
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{
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Index >>= 2;
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}
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break;
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}
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case 3:
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{
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if (L == 0 || S != 0)
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{
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Inst = AInst.Undefined;
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return;
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}
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Scale = Size;
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Replicate = true;
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break;
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}
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}
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this.SElems = SElems;
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this.Size = Scale;
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Extend64 = false;
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WBack = ((OpCode >> 23) & 0x1) != 0;
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RegisterSize = Q != 0
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? ARegisterSize.SIMD128
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: ARegisterSize.SIMD64;
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}
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}
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} |