Ryujinx/ARMeilleure/IntermediateRepresentation
riperiperi d7044b10a2
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
* Add CRC32 A32 instructions.

* Fix CRC32 instructions.

* Add CRC intrinsic and fast path.

Loop is currently unrolled, will look into adding temp vars after tests are added.

* Begin work on Crc tests

* Fix SSE4.2 path for CRC32C, finialize tests.

* Remove unused IR path.

* Fix spacing between prefix checks.

* This should be Src.

* PTC Version

* OpCodeTable Order

* Integer check improvement. Value and Crc can be either 32 or 64 size.

* This wasn't necessary...

* If size is 3, value type must be I64.

* Fix same src+dest handling for non crc intrinsics.

* Pre-fix (ha) issue with vex encodings
2020-07-13 20:48:14 +10:00
..
BasicBlock.cs
IIntrusiveListNode.cs
Instruction.cs Remove CpuId IR instruction (#1227) 2020-05-13 15:30:21 +10:00
Intrinsic.cs Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328) 2020-07-13 20:48:14 +10:00
IntrinsicOperation.cs
IntrusiveList.cs
MemoryOperand.cs CodeGen Optimisations (LSRA and Translator) (#978) 2020-03-18 22:44:32 +11:00
Multiplier.cs
Node.cs Fix Node Uses/Assignments (#1376) 2020-07-13 20:20:07 +10:00
Operand.cs Fix PPTC on Windows 7. (#1369) 2020-07-09 10:45:24 +10:00
OperandHelper.cs Fix PPTC on Windows 7. (#1369) 2020-07-09 10:45:24 +10:00
OperandKind.cs
OperandType.cs
Operation.cs CodeGen Optimisations (LSRA and Translator) (#978) 2020-03-18 22:44:32 +11:00
OperationHelper.cs CodeGen Optimisations (LSRA and Translator) (#978) 2020-03-18 22:44:32 +11:00
PhiNode.cs
Register.cs
RegisterType.cs