mirror of
https://github.com/GreemDev/Ryujinx
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5e0f8e8738
* Implement JIT Arm64 backend * PPTC version bump * Address some feedback from Arm64 JIT PR * Address even more PR feedback * Remove unused IsPageAligned function * Sync Qc flag before calls * Fix comment and remove unused enum * Address riperiperi PR feedback * Delete Breakpoint IR instruction that was only implemented for Arm64
65 lines
No EOL
1.9 KiB
C#
65 lines
No EOL
1.9 KiB
C#
using System;
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namespace ARMeilleure.IntermediateRepresentation
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{
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enum OperandType
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{
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None,
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I32,
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I64,
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FP32,
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FP64,
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V128
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}
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static class OperandTypeExtensions
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{
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public static bool IsInteger(this OperandType type)
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{
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return type == OperandType.I32 ||
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type == OperandType.I64;
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}
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public static RegisterType ToRegisterType(this OperandType type)
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{
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switch (type)
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{
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case OperandType.FP32: return RegisterType.Vector;
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case OperandType.FP64: return RegisterType.Vector;
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case OperandType.I32: return RegisterType.Integer;
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case OperandType.I64: return RegisterType.Integer;
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case OperandType.V128: return RegisterType.Vector;
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}
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throw new InvalidOperationException($"Invalid operand type \"{type}\".");
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}
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public static int GetSizeInBytes(this OperandType type)
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{
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switch (type)
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{
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case OperandType.FP32: return 4;
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case OperandType.FP64: return 8;
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case OperandType.I32: return 4;
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case OperandType.I64: return 8;
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case OperandType.V128: return 16;
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}
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throw new InvalidOperationException($"Invalid operand type \"{type}\".");
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}
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public static int GetSizeInBytesLog2(this OperandType type)
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{
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switch (type)
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{
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case OperandType.FP32: return 2;
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case OperandType.FP64: return 3;
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case OperandType.I32: return 2;
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case OperandType.I64: return 3;
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case OperandType.V128: return 4;
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}
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throw new InvalidOperationException($"Invalid operand type \"{type}\".");
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}
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}
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} |