mirror of
https://github.com/GreemDev/Ryujinx
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a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
153 lines
No EOL
5.3 KiB
C#
153 lines
No EOL
5.3 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.Instructions;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Memory;
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using ARMeilleure.State;
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using System.Collections.Generic;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Translation
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{
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class ArmEmitterContext : EmitterContext
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{
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private Dictionary<ulong, Operand> _labels;
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private OpCode _optOpLastCompare;
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private OpCode _optOpLastFlagSet;
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private Operand _optCmpTempN;
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private Operand _optCmpTempM;
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private Block _currBlock;
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public Block CurrBlock
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{
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get
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{
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return _currBlock;
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}
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set
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{
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_currBlock = value;
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ResetBlockState();
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}
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}
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public OpCode CurrOp { get; set; }
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public MemoryManager Memory { get; }
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public Aarch32Mode Mode { get; }
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public ArmEmitterContext(MemoryManager memory, Aarch32Mode mode)
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{
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Memory = memory;
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Mode = mode;
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_labels = new Dictionary<ulong, Operand>();
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}
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public Operand GetLabel(ulong address)
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{
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if (!_labels.TryGetValue(address, out Operand label))
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{
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label = Label();
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_labels.Add(address, label);
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}
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return label;
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}
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public void MarkComparison(Operand n, Operand m)
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{
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_optOpLastCompare = CurrOp;
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_optCmpTempN = Copy(n);
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_optCmpTempM = Copy(m);
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}
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public void MarkFlagSet(PState stateFlag)
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{
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// Set this only if any of the NZCV flag bits were modified.
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// This is used to ensure that when emiting a direct IL branch
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// instruction for compare + branch sequences, we're not expecting
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// to use comparison values from an old instruction, when in fact
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// the flags were already overwritten by another instruction further along.
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if (stateFlag >= PState.VFlag)
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{
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_optOpLastFlagSet = CurrOp;
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}
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}
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private void ResetBlockState()
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{
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_optOpLastCompare = null;
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_optOpLastFlagSet = null;
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}
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public Operand TryGetComparisonResult(Condition condition)
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{
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if (_optOpLastCompare == null || _optOpLastCompare != _optOpLastFlagSet)
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{
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return null;
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}
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Operand n = _optCmpTempN;
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Operand m = _optCmpTempM;
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InstName cmpName = _optOpLastCompare.Instruction.Name;
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if (cmpName == InstName.Subs)
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{
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switch (condition)
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{
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case Condition.Eq: return ICompareEqual (n, m);
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case Condition.Ne: return ICompareNotEqual (n, m);
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case Condition.GeUn: return ICompareGreaterOrEqualUI(n, m);
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case Condition.LtUn: return ICompareLessUI (n, m);
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case Condition.GtUn: return ICompareGreaterUI (n, m);
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case Condition.LeUn: return ICompareLessOrEqualUI (n, m);
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case Condition.Ge: return ICompareGreaterOrEqual (n, m);
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case Condition.Lt: return ICompareLess (n, m);
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case Condition.Gt: return ICompareGreater (n, m);
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case Condition.Le: return ICompareLessOrEqual (n, m);
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}
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}
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else if (cmpName == InstName.Adds && _optOpLastCompare is IOpCodeAluImm op)
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{
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// There are several limitations that needs to be taken into account for CMN comparisons:
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// - The unsigned comparisons are not valid, as they depend on the
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// carry flag value, and they will have different values for addition and
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// subtraction. For addition, it's carry, and for subtraction, it's borrow.
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// So, we need to make sure we're not doing a unsigned compare for the CMN case.
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// - We can only do the optimization for the immediate variants,
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// because when the second operand value is exactly INT_MIN, we can't
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// negate the value as theres no positive counterpart.
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// Such invalid values can't be encoded on the immediate encodings.
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if (op.RegisterSize == RegisterSize.Int32)
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{
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m = Const((int)-op.Immediate);
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}
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else
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{
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m = Const(-op.Immediate);
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}
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switch (condition)
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{
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case Condition.Eq: return ICompareEqual (n, m);
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case Condition.Ne: return ICompareNotEqual (n, m);
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case Condition.Ge: return ICompareGreaterOrEqual(n, m);
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case Condition.Lt: return ICompareLess (n, m);
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case Condition.Gt: return ICompareGreater (n, m);
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case Condition.Le: return ICompareLessOrEqual (n, m);
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}
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}
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return null;
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}
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}
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} |