mirror of
https://github.com/GreemDev/Ryujinx
synced 2024-11-30 05:22:08 +01:00
b1b6f294f2
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure 😩
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
319 lines
11 KiB
C#
319 lines
11 KiB
C#
#define SimdMemory32
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using ARMeilleure.State;
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using NUnit.Framework;
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using System;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdMemory32")]
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public sealed class CpuTestSimdMemory32 : CpuTest32
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{
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#if SimdMemory32
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private const int RndCntImm = 2;
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private uint[] LDSTModes =
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{
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// LD1
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0b0111,
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0b1010,
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0b0110,
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0b0010,
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// LD2
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0b1000,
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0b1001,
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0b0011,
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// LD3
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0b0100,
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0b0101,
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// LD4
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0b0000,
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0b0001
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};
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[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (single n element structure)")]
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public void Vldn_Single([Values(0u, 1u, 2u)] uint size,
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[Values(0u, 13u)] uint rn,
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[Values(1u, 13u, 15u)] uint rm,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
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[Range(0u, 7u)] uint index,
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[Range(0u, 3u)] uint n,
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[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
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opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15);
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uint index_align = (index << (int)(1 + size)) & 15;
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opcode |= (index_align) << 4;
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
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SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (all lanes)")]
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public void Vldn_All([Values(0u, 13u)] uint rn,
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[Values(1u, 13u, 15u)] uint rm,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
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[Range(0u, 3u)] uint n,
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[Range(0u, 2u)] uint size,
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[Values] bool t,
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[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
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opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15);
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
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if (t) opcode |= 1 << 5;
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SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
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public void Vldn_Pair([Values(0u, 1u, 2u, 3u)] uint size,
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[Values(0u, 13u)] uint rn,
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[Values(1u, 13u, 15u)] uint rm,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
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[Range(0u, 3u)] uint mode,
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[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
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opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSTn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (single n element structure)")]
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public void Vstn_Single([Values(0u, 1u, 2u)] uint size,
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[Values(0u, 13u)] uint rn,
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[Values(1u, 13u, 15u)] uint rm,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
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[Range(0u, 7u)] uint index,
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[Range(0u, 3u)] uint n,
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[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
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uint opcode = 0xf4800000u; // VST1.8 {D0[0]}, [R0], R0
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opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15);
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uint index_align = (index << (int)(1 + size)) & 15;
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opcode |= (index_align) << 4;
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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opcode |= (n & 3) << 8; // ST1 is 0, ST2 is 1 etc.
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SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSTn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (multiple n element structures)")]
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public void Vstn_Pair([Values(0u, 1u, 2u, 3u)] uint size,
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[Values(0u, 13u)] uint rn,
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[Values(1u, 13u, 15u)] uint rm,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
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[Range(0u, 3u)] uint mode,
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[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
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uint opcode = 0xf4000000u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
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opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VLDM.<size> <Rn>{!}, <d/sreglist>")]
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public void Vldm([Values(0u, 13u)] uint rn,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
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[Range(0u, 2u)] uint mode,
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[Values(0x1u, 0x32u)] [Random(2u, 31u, RndCntImm)] uint regs,
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[Values] bool single)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
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uint[] vldmModes = {
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// Note: 3rd 0 leaves a space for "D".
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0b0100, // Increment after.
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0b0101, // Increment after. (!)
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0b1001 // Decrement before. (!)
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};
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opcode |= ((vldmModes[mode] & 15) << 21);
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opcode |= ((rn & 15) << 16);
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opcode |= ((vd & 0x10) << 18);
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opcode |= ((vd & 0xf) << 12);
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opcode |= ((uint)(single ? 0 : 1) << 8);
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if (!single) regs = (regs << 1); // Low bit must be 0 - must be even number of registers.
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uint regSize = single ? 1u : 2u;
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if (vd + (regs / regSize) > 32) // Can't address further than S31 or D31.
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{
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regs -= (vd + (regs / regSize)) - 32;
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}
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if (regs / regSize > 16) // Can't do more than 16 registers at a time.
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{
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regs = 16 * regSize;
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}
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opcode |= regs & 0xff;
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SingleOpcode(opcode, r0: 0x2500, sp: 0x2500);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VLDR.<size> <Sd>, [<Rn> {, #{+/-}<imm>}]")]
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public void Vldr([Values(2u, 3u)] uint size, // FP16 is not supported for now
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[Values(0u)] uint rn,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd,
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[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm,
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[Values] bool sub)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
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opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
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if (sub)
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{
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opcode &= ~(uint)(1 << 23);
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}
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if (size == 2)
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{
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opcode |= ((sd & 0x1) << 22);
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opcode |= ((sd & 0x1e) << 11);
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}
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else
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{
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opcode |= ((sd & 0x10) << 18);
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opcode |= ((sd & 0xf) << 12);
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}
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opcode |= imm & 0xff;
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SingleOpcode(opcode, r0: 0x2500);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSTR.<size> <Sd>, [<Rn> {, #{+/-}<imm>}]")]
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public void Vstr([Values(2u, 3u)] uint size, // FP16 is not supported for now
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[Values(0u)] uint rn,
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[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint sd,
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[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint imm,
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[Values] bool sub)
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{
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var data = GenerateVectorSequence(0x1000);
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SetWorkingMemory(data);
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uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
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opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
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if (sub)
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{
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opcode &= ~(uint)(1 << 23);
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}
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if (size == 2)
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{
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opcode |= ((sd & 0x1) << 22);
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opcode |= ((sd & 0x1e) << 11);
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}
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else
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{
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opcode |= ((sd & 0x10) << 18);
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opcode |= ((sd & 0xf) << 12);
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}
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opcode |= imm & 0xff;
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(V128 vec1, V128 vec2, _, _) = GenerateTestVectors();
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SingleOpcode(opcode, r0: 0x2500, v0: vec1, v1: vec2);
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CompareAgainstUnicorn();
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}
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private (V128, V128, V128, V128) GenerateTestVectors()
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{
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return (
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new V128(-12.43f, 1872.23f, 4456.23f, -5622.2f),
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new V128(0.0f, float.NaN, float.PositiveInfinity, float.NegativeInfinity),
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new V128(1.23e10f, -0.0f, -0.123f, 0.123f),
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new V128(float.Epsilon, 3.5f, 925.23f, -104.9f)
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);
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}
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private byte[] GenerateVectorSequence(int length)
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{
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int floatLength = length >> 2;
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float[] data = new float[floatLength];
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for (int i = 0; i < floatLength; i++)
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{
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data[i] = i + (i / 9f);
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}
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var result = new byte[length];
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Buffer.BlockCopy(data, 0, result, 0, result.Length);
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return result;
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}
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#endif
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}
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}
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