mirror of
https://github.com/GreemDev/Ryujinx
synced 2024-11-22 17:56:59 +01:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
138 lines
No EOL
2.6 KiB
C#
138 lines
No EOL
2.6 KiB
C#
namespace ARMeilleure.IntermediateRepresentation
|
|
{
|
|
enum Intrinsic
|
|
{
|
|
X86Addpd,
|
|
X86Addps,
|
|
X86Addsd,
|
|
X86Addss,
|
|
X86Andnpd,
|
|
X86Andnps,
|
|
X86Cmppd,
|
|
X86Cmpps,
|
|
X86Cmpsd,
|
|
X86Cmpss,
|
|
X86Comisdeq,
|
|
X86Comisdge,
|
|
X86Comisdlt,
|
|
X86Comisseq,
|
|
X86Comissge,
|
|
X86Comisslt,
|
|
X86Cvtdq2pd,
|
|
X86Cvtdq2ps,
|
|
X86Cvtpd2dq,
|
|
X86Cvtpd2ps,
|
|
X86Cvtps2dq,
|
|
X86Cvtps2pd,
|
|
X86Cvtsd2si,
|
|
X86Cvtsd2ss,
|
|
X86Cvtss2sd,
|
|
X86Divpd,
|
|
X86Divps,
|
|
X86Divsd,
|
|
X86Divss,
|
|
X86Haddpd,
|
|
X86Haddps,
|
|
X86Maxpd,
|
|
X86Maxps,
|
|
X86Maxsd,
|
|
X86Maxss,
|
|
X86Minpd,
|
|
X86Minps,
|
|
X86Minsd,
|
|
X86Minss,
|
|
X86Movhlps,
|
|
X86Movlhps,
|
|
X86Mulpd,
|
|
X86Mulps,
|
|
X86Mulsd,
|
|
X86Mulss,
|
|
X86Paddb,
|
|
X86Paddd,
|
|
X86Paddq,
|
|
X86Paddw,
|
|
X86Pand,
|
|
X86Pandn,
|
|
X86Pavgb,
|
|
X86Pavgw,
|
|
X86Pblendvb,
|
|
X86Pcmpeqb,
|
|
X86Pcmpeqd,
|
|
X86Pcmpeqq,
|
|
X86Pcmpeqw,
|
|
X86Pcmpgtb,
|
|
X86Pcmpgtd,
|
|
X86Pcmpgtq,
|
|
X86Pcmpgtw,
|
|
X86Pmaxsb,
|
|
X86Pmaxsd,
|
|
X86Pmaxsw,
|
|
X86Pmaxub,
|
|
X86Pmaxud,
|
|
X86Pmaxuw,
|
|
X86Pminsb,
|
|
X86Pminsd,
|
|
X86Pminsw,
|
|
X86Pminub,
|
|
X86Pminud,
|
|
X86Pminuw,
|
|
X86Pmovsxbw,
|
|
X86Pmovsxdq,
|
|
X86Pmovsxwd,
|
|
X86Pmovzxbw,
|
|
X86Pmovzxdq,
|
|
X86Pmovzxwd,
|
|
X86Pmulld,
|
|
X86Pmullw,
|
|
X86Popcnt,
|
|
X86Por,
|
|
X86Pshufb,
|
|
X86Pslld,
|
|
X86Pslldq,
|
|
X86Psllq,
|
|
X86Psllw,
|
|
X86Psrad,
|
|
X86Psraw,
|
|
X86Psrld,
|
|
X86Psrlq,
|
|
X86Psrldq,
|
|
X86Psrlw,
|
|
X86Psubb,
|
|
X86Psubd,
|
|
X86Psubq,
|
|
X86Psubw,
|
|
X86Punpckhbw,
|
|
X86Punpckhdq,
|
|
X86Punpckhqdq,
|
|
X86Punpckhwd,
|
|
X86Punpcklbw,
|
|
X86Punpckldq,
|
|
X86Punpcklqdq,
|
|
X86Punpcklwd,
|
|
X86Pxor,
|
|
X86Rcpps,
|
|
X86Rcpss,
|
|
X86Roundpd,
|
|
X86Roundps,
|
|
X86Roundsd,
|
|
X86Roundss,
|
|
X86Rsqrtps,
|
|
X86Rsqrtss,
|
|
X86Shufpd,
|
|
X86Shufps,
|
|
X86Sqrtpd,
|
|
X86Sqrtps,
|
|
X86Sqrtsd,
|
|
X86Sqrtss,
|
|
X86Subpd,
|
|
X86Subps,
|
|
X86Subsd,
|
|
X86Subss,
|
|
X86Unpckhpd,
|
|
X86Unpckhps,
|
|
X86Unpcklpd,
|
|
X86Unpcklps,
|
|
X86Xorpd,
|
|
X86Xorps
|
|
}
|
|
} |