mirror of
https://github.com/alsa-project/alsa-utils
synced 2025-01-09 21:46:53 +01:00
451afcd37a
This patch adds the 3.0 format that is used for the PTL ACE3.x platform. Blob 3.0 is based on blob 1.5 but it adds DMA control registers settings and has some changes in registers bitfields. This patch also fixes some compile warnings when NHLT_DEBUG is set for comparing int with unsigned in ssp-debug.c for code for all blobs variants. Closes: https://github.com/alsa-project/alsa-utils/pull/276 Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
307 lines
12 KiB
C
307 lines
12 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Intel Corporation. All rights reserved.
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//
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// Author: Jaska Uimonen <jaska.uimonen@linux.intel.com>
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#include "aconfig.h"
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#include <stdio.h>
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#include <stdint.h>
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#include <alsa/global.h>
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#include "ssp-debug.h"
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#include "../intel-nhlt.h"
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#ifdef NHLT_DEBUG
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static void ssp_print_blob10(struct intel_ssp_params *ssp, int i)
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{
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struct ssp_intel_config_data *blob;
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int ssp_index = ssp->ssp_count;
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int j;
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blob = &ssp->ssp_blob[ssp_index][i];
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fprintf(stdout, "gateway_attributes %u\n", blob->gateway_attributes);
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for (j = 0; j < SSP_TS_GROUP_SIZE; j++)
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fprintf(stdout, "ts_group[%d] 0x%08x\n", j, blob->ts_group[j]);
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fprintf(stdout, "ssc0 0x%08x\n", blob->ssc0);
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fprintf(stdout, "ssc1 0x%08x\n", blob->ssc1);
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fprintf(stdout, "sscto 0x%08x\n", blob->sscto);
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fprintf(stdout, "sspsp 0x%08x\n", blob->sspsp);
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fprintf(stdout, "sstsa 0x%08x\n", blob->sstsa);
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fprintf(stdout, "ssrsa 0x%08x\n", blob->ssrsa);
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fprintf(stdout, "ssc2 0x%08x\n", blob->ssc2);
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fprintf(stdout, "sspsp2 0x%08x\n", blob->sspsp2);
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fprintf(stdout, "ssc3 0x%08x\n", blob->ssc3);
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fprintf(stdout, "ssioc 0x%08x\n", blob->ssioc);
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fprintf(stdout, "mdivc 0x%08x\n", blob->mdivc);
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fprintf(stdout, "mdivr 0x%08x\n", blob->mdivr);
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}
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static void ssp_print_blob15(struct intel_ssp_params *ssp, int i)
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{
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struct ssp_intel_config_data_1_5 *blob15;
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int ssp_index = ssp->ssp_count;
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uint32_t j;
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blob15 = &ssp->ssp_blob_1_5[ssp_index][i];
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fprintf(stdout, "gateway_attributes %u\n", blob15->gateway_attributes);
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fprintf(stdout, "version %u\n", blob15->version);
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fprintf(stdout, "size %u\n", blob15->size);
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for (j = 0; j < SSP_TS_GROUP_SIZE; j++)
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fprintf(stdout, "ts_group[%d] 0x%08x\n", j, blob15->ts_group[j]);
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fprintf(stdout, "ssc0 0x%08x\n", blob15->ssc0);
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fprintf(stdout, "ssc1 0x%08x\n", blob15->ssc1);
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fprintf(stdout, "sscto 0x%08x\n", blob15->sscto);
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fprintf(stdout, "sspsp 0x%08x\n", blob15->sspsp);
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fprintf(stdout, "sstsa 0x%08x\n", blob15->sstsa);
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fprintf(stdout, "ssrsa 0x%08x\n", blob15->ssrsa);
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fprintf(stdout, "ssc2 0x%08x\n", blob15->ssc2);
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fprintf(stdout, "sspsp2 0x%08x\n", blob15->sspsp2);
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fprintf(stdout, "ssc3 0x%08x\n", blob15->ssc3);
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fprintf(stdout, "ssioc 0x%08x\n", blob15->ssioc);
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fprintf(stdout, "mdivc 0x%08x\n", blob15->mdivctlr);
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fprintf(stdout, "mdivr count 0x%08x\n", blob15->mdivrcnt);
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for (j = 0; j < blob15->mdivrcnt; j++)
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fprintf(stdout, "mdivr 0x%08x\n",
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ssp->ssp_prm[ssp_index].mdivr[i].mdivrs[j]);
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}
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static void ssp_print_blob30(struct intel_ssp_params *ssp, int i)
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{
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struct ssp_intel_config_data_3_0 *blob30;
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int ssp_index = ssp->ssp_count;
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uint32_t j;
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blob30 = &ssp->ssp_blob_3_0[ssp_index][i];
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fprintf(stdout, "gateway_attributes %u\n", blob30->gateway_attributes);
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fprintf(stdout, "version %u\n", blob30->version);
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fprintf(stdout, "size %u\n", blob30->size);
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for (j = 0; j < SSP_TS_GROUP_SIZE; j++)
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fprintf(stdout, "ts_group[%d] 0x%08x\n", j, blob30->ts_group[j]);
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fprintf(stdout, "ssc0 0x%08x\n", blob30->ssc0);
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fprintf(stdout, "ssc1 0x%08x\n", blob30->ssc1);
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fprintf(stdout, "sscto 0x%08x\n", blob30->sscto);
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fprintf(stdout, "sspsp 0x%08x\n", blob30->sspsp);
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fprintf(stdout, "ssc2 0x%08x\n", blob30->ssc2);
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fprintf(stdout, "sspsp2 0x%08x\n", blob30->sspsp2);
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fprintf(stdout, "rsvd2 0x%08x\n", blob30->rsvd2);
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fprintf(stdout, "ssioc 0x%08x\n", blob30->ssioc);
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for (j = 0; j < I2SIPCMC; j++) {
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fprintf(stdout, "rx_dir[%d] 0x%08x\n", j * 2, (uint32_t)(blob30->rx_dir[j].ssmidytsa & 0xffffffff));
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fprintf(stdout, "rx_dir[%d] 0x%08x\n", j * 2 + 1, (uint32_t)(blob30->rx_dir[j].ssmidytsa >> 32));
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}
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for (j = 0; j < I2SOPCMC; j++) {
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fprintf(stdout, "tx_dir[%d] 0x%08x\n", j * 2, (uint32_t)(blob30->tx_dir[j].ssmodytsa & 0xffffffff));
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fprintf(stdout, "tx_dir[%d] 0x%08x\n", j * 2 + 1, (uint32_t)(blob30->tx_dir[j].ssmodytsa >> 32));
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}
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fprintf(stdout, "mdivc 0x%08x\n", blob30->mdivctlr);
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fprintf(stdout, "mdivr count 0x%08x\n", blob30->mdivrcnt);
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for (j = 0; j < blob30->mdivrcnt; j++)
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fprintf(stdout, "mdivr 0x%08x\n",
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ssp->ssp_prm[ssp_index].mdivr[i].mdivrs[j]);
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}
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void ssp_print_calculated(struct intel_ssp_params *ssp)
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{
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struct ssp_aux_blob *blob_aux;
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int ssp_index = ssp->ssp_count;
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uint32_t *ptr;
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uint32_t i, j;
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fprintf(stdout, "printing ssp nhlt calculated data:\n");
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/* top level struct */
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fprintf(stdout, "ssp index %d\n", ssp_index);
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fprintf(stdout, "ssp %d dai_index: %u\n", ssp_index, ssp->ssp_dai_index[ssp_index]);
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fprintf(stdout, "ssp blob version %u\n", ssp->ssp_prm[ssp_index].version);
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fprintf(stdout, "ssp %d hw_config_count: %u\n", ssp_index,
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ssp->ssp_hw_config_count[ssp_index]);
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fprintf(stdout, "\n");
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for (i = 0; i < ssp->ssp_hw_config_count[ssp_index]; i++) {
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fprintf(stdout, "ssp blob %d hw_config %d\n", ssp->ssp_count, i);
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switch (ssp->ssp_prm[ssp_index].version) {
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case SSP_BLOB_VER_1_5:
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ssp_print_blob15(ssp, i);
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break;
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case SSP_BLOB_VER_3_0:
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ssp_print_blob30(ssp, i);
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break;
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default:
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ssp_print_blob10(ssp, i);
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}
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blob_aux = (struct ssp_aux_blob *)&(ssp->ssp_blob_ext[ssp_index][i]);
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fprintf(stdout, "aux_blob size %u\n", blob_aux->size);
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for (j = 0; j < blob_aux->size; j += 4) {
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ptr = (uint32_t *)&(blob_aux->aux_blob[j]);
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fprintf(stdout, "aux_blob %d 0x%08x\n", j, *ptr);
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}
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fprintf(stdout, "\n");
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}
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fprintf(stdout, "\n");
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}
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void ssp_print_internal(struct intel_ssp_params *ssp)
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{
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struct ssp_aux_config_link *link;
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struct ssp_aux_config_sync *sync;
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struct ssp_aux_config_ext *ext;
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struct ssp_aux_config_run *run;
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struct ssp_aux_config_clk *clk;
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struct ssp_aux_config_mn *mn;
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struct ssp_aux_config_tr *tr;
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struct ssp_config_dai *dai;
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struct ssp_config_hw *hw_conf;
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uint32_t enabled;
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uint32_t i, j;
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dai = &ssp->ssp_prm[ssp->ssp_count];
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fprintf(stdout, "printing ssp nhlt internal data:\n");
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fprintf(stdout, "io_clk %u\n", dai->io_clk);
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fprintf(stdout, "dai_index %u\n", dai->dai_index);
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fprintf(stdout, "mclk_id %u\n", dai->mclk_id);
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fprintf(stdout, "sample_valid_bits %u\n", dai->sample_valid_bits);
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fprintf(stdout, "mclk_direction %u\n", dai->mclk_direction);
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fprintf(stdout, "frame_pulse_width %u\n", dai->frame_pulse_width);
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fprintf(stdout, "tdm_per_slot_padding_flag %u\n", dai->tdm_per_slot_padding_flag);
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fprintf(stdout, "clks_control %u\n", dai->clks_control);
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fprintf(stdout, "quirks %u\n", dai->quirks);
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fprintf(stdout, "bclk_delay %u\n", dai->bclk_delay);
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fprintf(stdout, "version %u\n", dai->version);
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fprintf(stdout, "\n");
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fprintf(stdout, "hw_config_count %u\n", ssp->ssp_hw_config_count[ssp->ssp_count]);
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for (i = 0; i < ssp->ssp_hw_config_count[ssp->ssp_count]; i++) {
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hw_conf = &dai->hw_cfg[i];
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fprintf(stdout, "mclk_rate %u\n", hw_conf->mclk_rate);
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fprintf(stdout, "bclk_rate %u\n", hw_conf->bclk_rate);
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fprintf(stdout, "fsync_rate %u\n", hw_conf->fsync_rate);
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fprintf(stdout, "tdm_slots %u\n", hw_conf->tdm_slots);
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fprintf(stdout, "tdm_slot_width %u\n", hw_conf->tdm_slot_width);
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fprintf(stdout, "tx_slots %u\n", hw_conf->tx_slots);
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fprintf(stdout, "rx_slots %u\n", hw_conf->rx_slots);
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fprintf(stdout, "format %u\n", hw_conf->format);
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enabled = dai->aux_cfg[i].enabled;
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fprintf(stdout, "aux enabled %x\n", enabled);
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fprintf(stdout, "\n");
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mn = (struct ssp_aux_config_mn *)&(dai->aux_cfg[i].mn);
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clk = (struct ssp_aux_config_clk *)&(dai->aux_cfg[i].clk);
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tr = (struct ssp_aux_config_tr *)&(dai->aux_cfg[i].tr_start);
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tr = (struct ssp_aux_config_tr *)&(dai->aux_cfg[i].tr_stop);
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run = (struct ssp_aux_config_run *)&(dai->aux_cfg[i].run);
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sync = (struct ssp_aux_config_sync *)&(dai->aux_cfg[i].sync);
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ext = (struct ssp_aux_config_ext *)&(dai->aux_cfg[i].ext);
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link = (struct ssp_aux_config_link *)&(dai->aux_cfg[i].link);
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if (enabled & BIT(SSP_MN_DIVIDER_CONTROLS)) {
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fprintf(stdout, "aux mn m_div %u\n", mn->m_div);
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fprintf(stdout, "aux mn n_div %u\n", mn->n_div);
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fprintf(stdout, "\n");
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}
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if (enabled & BIT(SSP_DMA_CLK_CONTROLS)) {
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fprintf(stdout, "aux clk clock_warm_up %u\n", clk->clock_warm_up);
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fprintf(stdout, "aux clk mclk %u\n", clk->mclk);
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fprintf(stdout, "aux clk warm_up_ovr %u\n", clk->warm_up_ovr);
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fprintf(stdout, "aux clk clock_stop_delay %u\n", clk->clock_stop_delay);
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fprintf(stdout, "aux clk keep_running %u\n", clk->keep_running);
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fprintf(stdout, "aux clk keep_running %u\n", clk->clock_stop_ovr);
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fprintf(stdout, "\n");
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}
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if (enabled & BIT(SSP_DMA_TRANSMISSION_START)) {
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fprintf(stdout, "aux tr start sampling_frequency %u\n", tr->sampling_frequency);
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fprintf(stdout, "aux tr start bit_depth %u\n", tr->bit_depth);
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fprintf(stdout, "aux tr start channel_map %u\n", tr->channel_map);
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fprintf(stdout, "aux tr start channel_config %u\n", tr->channel_config);
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fprintf(stdout, "aux tr start interleaving_style %u\n", tr->interleaving_style);
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fprintf(stdout, "aux tr start number_of_channels %u\n", tr->number_of_channels);
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fprintf(stdout, "aux tr start valid_bit_depth %u\n", tr->valid_bit_depth);
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fprintf(stdout, "aux tr start sample_types %u\n", tr->sample_type);
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fprintf(stdout, "\n");
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}
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if (enabled & BIT(SSP_DMA_TRANSMISSION_STOP)) {
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fprintf(stdout, "aux tr start sampling_frequency %u\n", tr->sampling_frequency);
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fprintf(stdout, "aux tr start bit_depth %u\n", tr->bit_depth);
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fprintf(stdout, "aux tr start channel_map %u\n", tr->channel_map);
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fprintf(stdout, "aux tr start channel_config %u\n", tr->channel_config);
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fprintf(stdout, "aux tr start interleaving_style %u\n", tr->interleaving_style);
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fprintf(stdout, "aux tr start number_of_channels %u\n", tr->number_of_channels);
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fprintf(stdout, "aux tr start valid_bit_depth %u\n", tr->valid_bit_depth);
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fprintf(stdout, "aux tr start sample_types %u\n", tr->sample_type);
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fprintf(stdout, "\n");
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}
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if (enabled & BIT(SSP_DMA_ALWAYS_RUNNING_MODE)) {
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fprintf(stdout, "aux run always_run %u\n", run->always_run);
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fprintf(stdout, "\n");
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}
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if (enabled & BIT(SSP_DMA_SYNC_DATA)) {
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fprintf(stdout, "aux sync sync_denominator %u\n", sync->sync_denominator);
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fprintf(stdout, "aux sync count %u\n", sync->count);
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for (j = 0; j < sync->count; j++) {
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fprintf(stdout, "aux sync node_id %u\n", sync->nodes[j].node_id);
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fprintf(stdout, "aux sync sampling_rate %u\n", sync->nodes[j].sampling_rate);
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}
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fprintf(stdout, "\n");
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}
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if (enabled & BIT(SSP_DMA_CLK_CONTROLS_EXT)) {
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fprintf(stdout, "aux ext mclk_policy_override %u\n", ext->mclk_policy_override);
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fprintf(stdout, "aux ext mclk_always_running %u\n", ext->mclk_always_running);
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fprintf(stdout, "aux ext mclk_starts_on_gtw_init %u\n", ext->mclk_starts_on_gtw_init);
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fprintf(stdout, "aux ext mclk_starts_on_run %u\n", ext->mclk_starts_on_run);
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fprintf(stdout, "aux ext mclk_starts_on_pause %u\n", ext->mclk_starts_on_pause);
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fprintf(stdout, "aux ext mclk_stops_on_pause %u\n", ext->mclk_stops_on_pause);
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fprintf(stdout, "aux ext mclk_stops_on_reset %u\n", ext->mclk_stops_on_reset);
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fprintf(stdout, "aux ext bclk_policy_override %u\n", ext->bclk_policy_override);
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fprintf(stdout, "aux ext bclk_always_running %u\n", ext->bclk_always_running);
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fprintf(stdout, "aux ext bclk_starts_on_gtw_init %u\n", ext->bclk_starts_on_gtw_init);
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fprintf(stdout, "aux ext bclk_starts_on_run %u\n", ext->bclk_starts_on_run);
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fprintf(stdout, "aux ext bclk_starts_on_pause %u\n", ext->bclk_starts_on_pause);
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fprintf(stdout, "aux ext bclk_stops_on_pause %u\n", ext->bclk_stops_on_pause);
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fprintf(stdout, "aux ext bclk_stops_on_reset %u\n", ext->bclk_stops_on_reset);
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fprintf(stdout, "aux ext sync_policy_override %u\n", ext->sync_policy_override);
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fprintf(stdout, "aux ext sync_always_running %u\n", ext->sync_always_running);
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fprintf(stdout, "aux ext sync_starts_on_gtw_init %u\n", ext->sync_starts_on_gtw_init);
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fprintf(stdout, "aux ext sync_starts_on_run %u\n", ext->sync_starts_on_run);
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fprintf(stdout, "aux ext sync_starts_on_pause %u\n", ext->sync_starts_on_pause);
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fprintf(stdout, "aux ext sync_stops_on_pause %u\n", ext->sync_stops_on_pause);
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fprintf(stdout, "aux ext sync_stops_on_reset %u\n", ext->sync_stops_on_reset);
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fprintf(stdout, "\n");
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}
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if (enabled & BIT(SSP_LINK_CLK_SOURCE)) {
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fprintf(stdout, "aux link clock_source %u\n", link->clock_source);
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fprintf(stdout, "\n");
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}
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}
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fprintf(stdout, "\n");
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}
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#else /* NHLT_DEBUG */
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void ssp_print_internal(struct intel_ssp_params *ssp ATTRIBUTE_UNUSED) {}
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void ssp_print_calculated(struct intel_ssp_params *ssp ATTRIBUTE_UNUSED) {}
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#endif
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