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https://github.com/alsa-project/alsa-utils
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c57391dd26
There was a conceptual error in handling the separate ssp dais, so fix it. Fixes: https://github.com/alsa-project/alsa-utils/pull/164 Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
264 lines
7.7 KiB
C
264 lines
7.7 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Intel Corporation. All rights reserved.
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//
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// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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// Rander Wang <rander.wang@linux.intel.com>
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// Jaska Uimonen <jaska.uimonen@linux.intel.com>
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#ifndef __SSP_MACROS_H
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#define __SSP_MACROS_H
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#include "ssp-intel.h"
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#define SSP_MAX_DAIS 8
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#define SSP_MAX_HW_CONFIG 8
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#define SSP_TDM_MAX_SLOT_MAP_COUNT 8
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/* structs for gathering the ssp parameters from topology */
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struct ssp_config_hw {
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uint32_t mclk_rate;
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uint32_t bclk_rate;
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uint32_t fsync_rate;
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uint32_t tdm_slots;
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uint32_t tdm_slot_width;
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uint32_t tx_slots;
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uint32_t rx_slots;
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uint32_t format;
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};
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struct ssp_config_dai {
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uint32_t io_clk;
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uint32_t dai_index;
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uint16_t mclk_id;
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uint32_t sample_valid_bits;
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uint32_t mclk_direction;
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uint16_t frame_pulse_width;
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uint16_t tdm_per_slot_padding_flag;
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uint32_t clks_control;
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uint32_t quirks;
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uint32_t bclk_delay;
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uint8_t direction;
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struct ssp_config_hw hw_cfg[SSP_MAX_HW_CONFIG];
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};
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struct intel_ssp_params {
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/* structs to gather ssp params before calculations */
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struct ssp_config_dai ssp_prm[SSP_MAX_DAIS];
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uint32_t ssp_dai_index[SSP_MAX_DAIS];
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uint32_t ssp_hw_config_count[SSP_MAX_DAIS];
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int ssp_count;
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/* ssp vendor blob structs */
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struct ssp_intel_config_data ssp_blob[SSP_MAX_DAIS][SSP_MAX_HW_CONFIG];
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};
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#define SSP_CLOCK_XTAL_OSCILLATOR 0x0
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#define SSP_CLOCK_AUDIO_CARDINAL 0x1
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#define SSP_CLOCK_PLL_FIXED 0x2
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#define MCDSS(x) SET_BITS(17, 16, x)
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#define MNDSS(x) SET_BITS(21, 20, x)
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#define SSP_FMT_I2S 1 /**< I2S mode */
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#define SSP_FMT_RIGHT_J 2 /**< Right Justified mode */
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#define SSP_FMT_LEFT_J 3 /**< Left Justified mode */
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#define SSP_FMT_DSP_A 4 /**< L data MSB after FRM LRC */
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#define SSP_FMT_DSP_B 5 /**< L data MSB during FRM LRC */
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#define SSP_FMT_PDM 6 /**< Pulse density modulation */
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#define SSP_FMT_CONT (1 << 4) /**< continuous clock */
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#define SSP_FMT_GATED (0 << 4) /**< clock is gated */
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#define SSP_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */
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#define SSP_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
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#define SSP_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
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#define SSP_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
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#define SSP_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
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#define SSP_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
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#define SSP_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
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#define SSP_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
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#define SSP_FMT_FORMAT_MASK 0x000f
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#define SSP_FMT_CLOCK_MASK 0x00f0
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#define SSP_FMT_INV_MASK 0x0f00
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#define SSP_FMT_CLOCK_PROVIDER_MASK 0xf000
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/* SSCR0 bits */
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#define SSCR0_DSIZE(x) SET_BITS(3, 0, (x) - 1)
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#define SSCR0_FRF MASK(5, 4)
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#define SSCR0_MOT SET_BITS(5, 4, 0)
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#define SSCR0_TI SET_BITS(5, 4, 1)
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#define SSCR0_NAT SET_BITS(5, 4, 2)
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#define SSCR0_PSP SET_BITS(5, 4, 3)
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#define SSCR0_ECS BIT(6)
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#define SSCR0_SSE BIT(7)
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#define SSCR0_SCR_MASK MASK(19, 8)
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#define SSCR0_SCR(x) SET_BITS(19, 8, x)
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#define SSCR0_EDSS BIT(20)
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#define SSCR0_NCS BIT(21)
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#define SSCR0_RIM BIT(22)
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#define SSCR0_TIM BIT(23)
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#define SSCR0_FRDC(x) SET_BITS(26, 24, (x) - 1)
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#define SSCR0_ACS BIT(30)
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#define SSCR0_MOD BIT(31)
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/* SSCR1 bits */
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#define SSCR1_RIE BIT(0)
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#define SSCR1_TIE BIT(1)
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#define SSCR1_LBM BIT(2)
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#define SSCR1_SPO BIT(3)
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#define SSCR1_SPH BIT(4)
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#define SSCR1_MWDS BIT(5)
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#define SSCR1_TFT_MASK MASK(9, 6)
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#define SSCR1_TFT(x) SET_BITS(9, 6, (x) - 1)
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#define SSCR1_RFT_MASK MASK(13, 10)
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#define SSCR1_RFT(x) SET_BITS(13, 10, (x) - 1)
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#define SSCR1_EFWR BIT(14)
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#define SSCR1_STRF BIT(15)
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#define SSCR1_IFS BIT(16)
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#define SSCR1_PINTE BIT(18)
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#define SSCR1_TINTE BIT(19)
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#define SSCR1_RSRE BIT(20)
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#define SSCR1_TSRE BIT(21)
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#define SSCR1_TRAIL BIT(22)
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#define SSCR1_RWOT BIT(23)
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#define SSCR1_SFRMDIR BIT(24)
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#define SSCR1_SCLKDIR BIT(25)
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#define SSCR1_ECRB BIT(26)
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#define SSCR1_ECRA BIT(27)
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#define SSCR1_SCFR BIT(28)
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#define SSCR1_EBCEI BIT(29)
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#define SSCR1_TTE BIT(30)
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#define SSCR1_TTELP BIT(31)
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/* SSCR2 bits */
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#define SSCR2_URUN_FIX0 BIT(0)
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#define SSCR2_URUN_FIX1 BIT(1)
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#define SSCR2_SLV_EXT_CLK_RUN_EN BIT(2)
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#define SSCR2_CLK_DEL_EN BIT(3)
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#define SSCR2_UNDRN_FIX_EN BIT(6)
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#define SSCR2_FIFO_EMPTY_FIX_EN BIT(7)
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#define SSCR2_ASRC_CNTR_EN BIT(8)
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#define SSCR2_ASRC_CNTR_CLR BIT(9)
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#define SSCR2_ASRC_FRM_CNRT_EN BIT(10)
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#define SSCR2_ASRC_INTR_MASK BIT(11)
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#define SSCR2_TURM1 BIT(1)
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#define SSCR2_PSPSRWFDFD BIT(3)
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#define SSCR2_PSPSTWFDFD BIT(4)
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#define SSCR2_SDFD BIT(14)
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#define SSCR2_SDPM BIT(16)
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#define SSCR2_LJDFD BIT(17)
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#define SSCR2_MMRATF BIT(18)
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#define SSCR2_SMTATF BIT(19)
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/* SSR bits */
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#define SSSR_TNF BIT(2)
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#define SSSR_RNE BIT(3)
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#define SSSR_BSY BIT(4)
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#define SSSR_TFS BIT(5)
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#define SSSR_RFS BIT(6)
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#define SSSR_ROR BIT(7)
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#define SSSR_TUR BIT(21)
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/* SSPSP bits */
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#define SSPSP_SCMODE(x) SET_BITS(1, 0, x)
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#define SSPSP_SFRMP(x) SET_BIT(2, x)
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#define SSPSP_ETDS BIT(3)
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#define SSPSP_STRTDLY(x) SET_BITS(6, 4, x)
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#define SSPSP_DMYSTRT(x) SET_BITS(8, 7, x)
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#define SSPSP_SFRMDLY(x) SET_BITS(15, 9, x)
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#define SSPSP_SFRMWDTH(x) SET_BITS(21, 16, x)
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#define SSPSP_DMYSTOP(x) SET_BITS(24, 23, x)
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#define SSPSP_DMYSTOP_BITS 2
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#define SSPSP_DMYSTOP_MASK MASK(SSPSP_DMYSTOP_BITS - 1, 0)
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#define SSPSP_FSRT BIT(25)
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#define SSPSP_EDMYSTOP(x) SET_BITS(28, 26, x)
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#define SSPSP2 0x44
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#define SSPSP2_FEP_MASK 0xff
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#define SSCR3 0x48
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#define SSIOC 0x4C
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#define SSP_REG_MAX SSIOC
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/* SSTSA bits */
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#define SSTSA_SSTSA(x) SET_BITS(7, 0, x)
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#define SSTSA_TXEN BIT(8)
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/* SSRSA bits */
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#define SSRSA_SSRSA(x) SET_BITS(7, 0, x)
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#define SSRSA_RXEN BIT(8)
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/* SSCR3 bits */
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#define SSCR3_FRM_MST_EN BIT(0)
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#define SSCR3_I2S_MODE_EN BIT(1)
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#define SSCR3_I2S_FRM_POL(x) SET_BIT(2, x)
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#define SSCR3_I2S_TX_SS_FIX_EN BIT(3)
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#define SSCR3_I2S_RX_SS_FIX_EN BIT(4)
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#define SSCR3_I2S_TX_EN BIT(9)
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#define SSCR3_I2S_RX_EN BIT(10)
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#define SSCR3_CLK_EDGE_SEL BIT(12)
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#define SSCR3_STRETCH_TX BIT(14)
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#define SSCR3_STRETCH_RX BIT(15)
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#define SSCR3_MST_CLK_EN BIT(16)
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#define SSCR3_SYN_FIX_EN BIT(17)
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/* SSCR4 bits */
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#define SSCR4_TOT_FRM_PRD(x) ((x) << 7)
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/* SSCR5 bits */
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#define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
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#define SSCR5_FRM_POLARITY(x) SET_BIT(0, x)
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/* SFIFOTT bits */
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#define SFIFOTT_TX(x) ((x) - 1)
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#define SFIFOTT_RX(x) (((x) - 1) << 16)
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/* SFIFOL bits */
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#define SFIFOL_TFL(x) ((x) & 0xFFFF)
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#define SFIFOL_RFL(x) ((x) >> 16)
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#define SSTSA_TSEN BIT(8)
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#define SSRSA_RSEN BIT(8)
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#define SSCR3_TFL_MASK MASK(5, 0)
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#define SSCR3_RFL_MASK MASK(13, 8)
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#define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & MASK(5, 0))
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#define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & MASK(5, 0))
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#define SSCR3_TX(x) SET_BITS(21, 16, (x) - 1)
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#define SSCR3_RX(x) SET_BITS(29, 24, (x) - 1)
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#define SSIOC_TXDPDEB BIT(1)
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#define SSIOC_SFCR BIT(4)
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#define SSIOC_SCOE BIT(5)
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#define MAX_SSP_COUNT 8
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#define SSP_FIFO_DEPTH 16
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#define SSP_FIFO_WATERMARK 8
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#define SSP_INTEL_QUIRK_TINTE (1 << 0)
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#define SSP_INTEL_QUIRK_PINTE (1 << 1)
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#define SSP_INTEL_QUIRK_SMTATF (1 << 2)
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#define SSP_INTEL_QUIRK_MMRATF (1 << 3)
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#define SSP_INTEL_QUIRK_PSPSTWFDFD (1 << 4)
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#define SSP_INTEL_QUIRK_PSPSRWFDFD (1 << 5)
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#define SSP_INTEL_QUIRK_LBM (1 << 6)
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#define SSP_INTEL_FRAME_PULSE_WIDTH_MAX 38
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#define SSP_INTEL_SLOT_PADDING_MAX 31
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/* SSP clocks control settings */
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#define SSP_INTEL_MCLK_0_DISABLE BIT(0)
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#define SSP_INTEL_MCLK_1_DISABLE BIT(1)
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#define SSP_INTEL_CLKCTRL_MCLK_KA BIT(2)
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#define SSP_INTEL_CLKCTRL_BCLK_KA BIT(3)
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#define SSP_INTEL_CLKCTRL_FS_KA BIT(4)
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#define SSP_INTEL_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
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#endif /* __SSP_MACROS_H */
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