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https://github.com/alsa-project/alsa-utils
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1ad140f641
Intel ssp blob can have auxiliary controls catenated as tlv array at the
end of its "normal" data blob. These are needed in some platforms for
example to enable hardware clocks earlier than streaming starts.
In topology the auxiliary data classes are embedded into hw_config and
can be instantiated like:
Object.Base.hw_config."SSP0_0" {
id 0
mclk_freq 38400000
bclk_freq 256000
tdm_slot_width 16
format "DSP_A"
bclk "codec_provider"
fsync "codec_provider"
fsync_freq 16000
Object.Base.mn_config."MN_0" {
m_div 100
n_div 200
}
Object.Base.clk_config."CLK_0" {
clock_warm_up 1
mclk 2
warm_up_ovr 3
clock_stop_delay 4
keep_running 5
clock_stop_ovr 6
}
}
Fixes: https://github.com/alsa-project/alsa-utils/pull/184
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
102 lines
2.1 KiB
C
102 lines
2.1 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Intel Corporation. All rights reserved.
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//
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// Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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// Rander Wang <rander.wang@linux.intel.com>
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// Jaska Uimonen <jaska.uimonen@linux.intel.com>
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#ifndef __SSP_INTEL_H
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#define __SSP_INTEL_H
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#include <stdint.h>
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/* struct for intel ssp nhlt vendor specific blob generation */
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struct ssp_intel_config_data {
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uint32_t gateway_attributes;
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uint32_t ts_group[8];
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uint32_t ssc0;
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uint32_t ssc1;
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uint32_t sscto;
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uint32_t sspsp;
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uint32_t sstsa;
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uint32_t ssrsa;
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uint32_t ssc2;
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uint32_t sspsp2;
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uint32_t ssc3;
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uint32_t ssioc;
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uint32_t mdivc;
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uint32_t mdivr;
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} __attribute__((packed));
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#define SSP_BLOB_VER_1_5 0xEE000105
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struct ssp_intel_config_data_1_5 {
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uint32_t gateway_attributes;
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uint32_t version;
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uint32_t size;
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uint32_t ts_group[8];
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uint32_t ssc0;
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uint32_t ssc1;
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uint32_t sscto;
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uint32_t sspsp;
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uint32_t sstsa;
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uint32_t ssrsa;
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uint32_t ssc2;
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uint32_t sspsp2;
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uint32_t ssc3;
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uint32_t ssioc;
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uint32_t mdivctlr;
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uint32_t mdivrcnt;
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uint32_t mdivr[];
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} __attribute__((packed));
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struct ssp_intel_aux_tlv {
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uint32_t type;
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uint32_t size;
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uint32_t val[];
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} __attribute__((packed));
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struct ssp_intel_mn_ctl {
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uint32_t div_m;
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uint32_t div_n;
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} __attribute__((packed));
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struct ssp_intel_clk_ctl {
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uint32_t start;
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uint32_t stop;
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} __attribute__((packed));
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struct ssp_intel_tr_ctl {
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uint32_t sampling_frequency;
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uint32_t bit_depth;
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uint32_t channel_map;
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uint32_t channel_config;
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uint32_t interleaving_style;
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uint32_t format;
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} __attribute__((packed));
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struct ssp_intel_run_ctl {
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uint32_t enabled;
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} __attribute__((packed));
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struct ssp_intel_node_ctl {
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uint32_t node_id;
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uint32_t sampling_rate;
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} __attribute__((packed));
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struct ssp_intel_sync_ctl {
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uint32_t sync_denominator;
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uint32_t count;
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} __attribute__((packed));
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struct ssp_intel_ext_ctl {
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uint32_t ext_data;
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} __attribute__((packed));
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struct ssp_intel_link_ctl {
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uint32_t clock_source;
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} __attribute__((packed));
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#endif /* __SSP_INTEL_H */
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