296 lines
13 KiB
Text
296 lines
13 KiB
Text
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Freescale QUICC Engine Firmware Uploading
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-----------------------------------------
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(c) 2007 Timur Tabi <timur at freescale.com>,
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Freescale Semiconductor
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Table of Contents
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=================
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I - Software License for Firmware
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II - Microcode Availability
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III - Description and Terminology
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IV - Microcode Programming Details
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V - Firmware Structure Layout
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VI - Sample Code for Creating Firmware Files
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Revision Information
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====================
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November 30, 2007: Rev 1.0 - Initial version
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I - Software License for Firmware
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=================================
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Each firmware file comes with its own software license. For information on
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the particular license, please see the license text that is distributed with
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the firmware.
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II - Microcode Availability
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===========================
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Firmware files are distributed through various channels. Some are available on
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http://opensource.freescale.com. For other firmware files, please contact
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your Freescale representative or your operating system vendor.
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III - Description and Terminology
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================================
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In this document, the term 'microcode' refers to the sequence of 32-bit
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integers that compose the actual QE microcode.
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The term 'firmware' refers to a binary blob that contains the microcode as
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well as other data that
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1) describes the microcode's purpose
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2) describes how and where to upload the microcode
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3) specifies the values of various registers
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4) includes additional data for use by specific device drivers
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Firmware files are binary files that contain only a firmware.
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IV - Microcode Programming Details
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===================================
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The QE architecture allows for only one microcode present in I-RAM for each
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RISC processor. To replace any current microcode, a full QE reset (which
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disables the microcode) must be performed first.
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QE microcode is uploaded using the following procedure:
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1) The microcode is placed into I-RAM at a specific location, using the
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IRAM.IADD and IRAM.IDATA registers.
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2) The CERCR.CIR bit is set to 0 or 1, depending on whether the firmware
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needs split I-RAM. Split I-RAM is only meaningful for SOCs that have
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QEs with multiple RISC processors, such as the 8360. Splitting the I-RAM
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allows each processor to run a different microcode, effectively creating an
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asymmetric multiprocessing (AMP) system.
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3) The TIBCR trap registers are loaded with the addresses of the trap handlers
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in the microcode.
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4) The RSP.ECCR register is programmed with the value provided.
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5) If necessary, device drivers that need the virtual traps and extended mode
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data will use them.
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Virtual Microcode Traps
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These virtual traps are conditional branches in the microcode. These are
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"soft" provisional introduced in the ROMcode in order to enable higher
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flexibility and save h/w traps If new features are activated or an issue is
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being fixed in the RAM package utilizing they should be activated. This data
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structure signals the microcode which of these virtual traps is active.
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This structure contains 6 words that the application should copy to some
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specific been defined. This table describes the structure.
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---------------------------------------------------------------
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| Offset in | | Destination Offset | Size of |
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| array | Protocol | within PRAM | Operand |
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--------------------------------------------------------------|
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| 0 | Ethernet | 0xF8 | 4 bytes |
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| | interworking | | |
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---------------------------------------------------------------
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| 4 | ATM | 0xF8 | 4 bytes |
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| | interworking | | |
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---------------------------------------------------------------
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| 8 | PPP | 0xF8 | 4 bytes |
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| | interworking | | |
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---------------------------------------------------------------
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| 12 | Ethernet RX | 0x22 | 1 byte |
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| | Distributor Page | | |
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---------------------------------------------------------------
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| 16 | ATM Globtal | 0x28 | 1 byte |
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| | Params Table | | |
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---------------------------------------------------------------
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| 20 | Insert Frame | 0xF8 | 4 bytes |
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---------------------------------------------------------------
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Extended Modes
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This is a double word bit array (64 bits) that defines special functionality
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which has an impact on the softwarew drivers. Each bit has its own impact
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and has special instructions for the s/w associated with it. This structure is
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described in this table:
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-----------------------------------------------------------------------
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| Bit # | Name | Description |
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-----------------------------------------------------------------------
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| 0 | General | Indicates that prior to each host command |
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| | push command | given by the application, the software must |
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| | | assert a special host command (push command)|
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| | | CECDR = 0x00800000. |
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| | | CECR = 0x01c1000f. |
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-----------------------------------------------------------------------
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| 1 | UCC ATM | Indicates that after issuing ATM RX INIT |
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| | RX INIT | command, the host must issue another special|
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| | push command | command (push command) and immediately |
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| | | following that re-issue the ATM RX INIT |
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| | | command. (This makes the sequence of |
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| | | initializing the ATM receiver a sequence of |
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| | | three host commands) |
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| | | CECDR = 0x00800000. |
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| | | CECR = 0x01c1000f. |
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-----------------------------------------------------------------------
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| 2 | Add/remove | Indicates that following the specific host |
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| | command | command: "Add/Remove entry in Hash Lookup |
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| | validation | Table" used in Interworking setup, the user |
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| | | must issue another command. |
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| | | CECDR = 0xce000003. |
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| | | CECR = 0x01c10f58. |
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-----------------------------------------------------------------------
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| 3 | General push | Indicates that the s/w has to initialize |
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| | command | some pointers in the Ethernet thread pages |
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| | | which are used when Header Compression is |
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| | | activated. The full details of these |
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| | | pointers is located in the software drivers.|
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-----------------------------------------------------------------------
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| 4 | General push | Indicates that after issuing Ethernet TX |
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| | command | INIT command, user must issue this command |
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| | | for each SNUM of Ethernet TX thread. |
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| | | CECDR = 0x00800003. |
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| | | CECR = 0x7'b{0}, 8'b{Enet TX thread SNUM}, |
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| | | 1'b{1}, 12'b{0}, 4'b{1} |
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-----------------------------------------------------------------------
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| 5 - 31 | N/A | Reserved, set to zero. |
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-----------------------------------------------------------------------
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V - Firmware Structure Layout
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==============================
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QE microcode from Freescale is typically provided as a header file. This
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header file contains macros that define the microcode binary itself as well as
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some other data used in uploading that microcode. The format of these files
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do not lend themselves to simple inclusion into other code. Hence,
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the need for a more portable format. This section defines that format.
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Instead of distributing a header file, the microcode and related data are
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embedded into a binary blob. This blob is passed to the qe_upload_firmware()
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function, which parses the blob and performs everything necessary to upload
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the microcode.
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All integers are big-endian. See the comments for function
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qe_upload_firmware() for up-to-date implementation information.
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This structure supports versioning, where the version of the structure is
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embedded into the structure itself. To ensure forward and backwards
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compatibility, all versions of the structure must use the same 'qe_header'
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structure at the beginning.
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'header' (type: struct qe_header):
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The 'length' field is the size, in bytes, of the entire structure,
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including all the microcode embedded in it, as well as the CRC (if
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present).
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The 'magic' field is an array of three bytes that contains the letters
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'Q', 'E', and 'F'. This is an identifier that indicates that this
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structure is a QE Firmware structure.
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The 'version' field is a single byte that indicates the version of this
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structure. If the layout of the structure should ever need to be
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changed to add support for additional types of microcode, then the
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version number should also be changed.
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The 'id' field is a null-terminated string(suitable for printing) that
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identifies the firmware.
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The 'count' field indicates the number of 'microcode' structures. There
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must be one and only one 'microcode' structure for each RISC processor.
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Therefore, this field also represents the number of RISC processors for this
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SOC.
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The 'soc' structure contains the SOC numbers and revisions used to match
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the microcode to the SOC itself. Normally, the microcode loader should
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check the data in this structure with the SOC number and revisions, and
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only upload the microcode if there's a match. However, this check is not
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made on all platforms.
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Although it is not recommended, you can specify '0' in the soc.model
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field to skip matching SOCs altogether.
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The 'model' field is a 16-bit number that matches the actual SOC. The
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'major' and 'minor' fields are the major and minor revision numbrs,
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respectively, of the SOC.
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For example, to match the 8323, revision 1.0:
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soc.model = 8323
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soc.major = 1
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soc.minor = 0
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'padding' is neccessary for structure alignment. This field ensures that the
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'extended_modes' field is aligned on a 64-bit boundary.
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'extended_modes' is a bitfield that defines special functionality which has an
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impact on the device drivers. Each bit has its own impact and has special
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instructions for the driver associated with it. This field is stored in
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the QE library and available to any driver that calles qe_get_firmware_info().
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'vtraps' is an array of 8 words that contain virtual trap values for each
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virtual traps. As with 'extended_modes', this field is stored in the QE
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library and available to any driver that calles qe_get_firmware_info().
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'microcode' (type: struct qe_microcode):
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For each RISC processor there is one 'microcode' structure. The first
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'microcode' structure is for the first RISC, and so on.
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The 'id' field is a null-terminated string suitable for printing that
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identifies this particular microcode.
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'traps' is an array of 16 words that contain hardware trap values
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for each of the 16 traps. If trap[i] is 0, then this particular
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trap is to be ignored (i.e. not written to TIBCR[i]). The entire value
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is written as-is to the TIBCR[i] register, so be sure to set the EN
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and T_IBP bits if necessary.
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'eccr' is the value to program into the ECCR register.
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'iram_offset' is the offset into IRAM to start writing the
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microcode.
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'count' is the number of 32-bit words in the microcode.
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'code_offset' is the offset, in bytes, from the beginning of this
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structure where the microcode itself can be found. The first
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microcode binary should be located immediately after the 'microcode'
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array.
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'major', 'minor', and 'revision' are the major, minor, and revision
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version numbers, respectively, of the microcode. If all values are 0,
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then these fields are ignored.
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'reserved' is necessary for structure alignment. Since 'microcode'
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is an array, the 64-bit 'extended_modes' field needs to be aligned
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on a 64-bit boundary, and this can only happen if the size of
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'microcode' is a multiple of 8 bytes. To ensure that, we add
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'reserved'.
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After the last microcode is a 32-bit CRC. It can be calculated using
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this algorithm:
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u32 crc32(const u8 *p, unsigned int len)
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{
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unsigned int i;
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u32 crc = 0;
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while (len--) {
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crc ^= *p++;
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for (i = 0; i < 8; i++)
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crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
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}
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return crc;
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}
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VI - Sample Code for Creating Firmware Files
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============================================
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A Python program that creates firmware binaries from the header files normally
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distributed by Freescale can be found on http://opensource.freescale.com.
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