2008-04-16 03:56:35 +02:00
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/*
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* linux/arch/arm/mach-ep93xx/gpio.c
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*
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* Generic EP93xx GPIO handling
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*
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* Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
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*
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* Based on code originally from:
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* linux/arch/arm/mach-ep93xx/core.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2010-02-23 21:41:17 +01:00
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#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
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2008-04-16 03:56:35 +02:00
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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2008-09-06 13:10:45 +02:00
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#include <linux/io.h>
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2009-06-26 22:39:27 +02:00
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#include <linux/gpio.h>
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2009-07-15 22:31:46 +02:00
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#include <linux/irq.h>
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2008-04-16 03:56:35 +02:00
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2009-06-26 22:39:27 +02:00
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#include <mach/hardware.h>
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2008-04-16 03:56:35 +02:00
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2010-02-23 21:41:17 +01:00
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/*************************************************************************
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2010-04-06 23:46:16 +02:00
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* Interrupt handling for EP93xx on-chip GPIOs
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2010-02-23 21:41:17 +01:00
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*************************************************************************/
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static unsigned char gpio_int_unmasked[3];
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static unsigned char gpio_int_enabled[3];
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static unsigned char gpio_int_type1[3];
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static unsigned char gpio_int_type2[3];
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static unsigned char gpio_int_debounce[3];
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/* Port ordering is: A B F */
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static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
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static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
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static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
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static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
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static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
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2010-04-06 23:46:16 +02:00
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static void ep93xx_gpio_update_int_params(unsigned port)
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2010-02-23 21:41:17 +01:00
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{
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BUG_ON(port > 2);
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__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
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__raw_writeb(gpio_int_type2[port],
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EP93XX_GPIO_REG(int_type2_register_offset[port]));
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__raw_writeb(gpio_int_type1[port],
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EP93XX_GPIO_REG(int_type1_register_offset[port]));
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__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
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EP93XX_GPIO_REG(int_en_register_offset[port]));
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}
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2010-04-06 23:46:16 +02:00
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static inline void ep93xx_gpio_int_mask(unsigned line)
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2010-02-23 21:41:17 +01:00
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{
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gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
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}
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void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (enable)
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gpio_int_debounce[port] |= port_mask;
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else
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gpio_int_debounce[port] &= ~port_mask;
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__raw_writeb(gpio_int_debounce[port],
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EP93XX_GPIO_REG(int_debounce_register_offset[port]));
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}
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EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
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static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned char status;
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int i;
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status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
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generic_handle_irq(gpio_irq);
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}
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}
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status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
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generic_handle_irq(gpio_irq);
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}
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}
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}
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static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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/*
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* map discontiguous hw irq range to continous sw irq range:
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*
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* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
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*/
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int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
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generic_handle_irq(gpio_irq);
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}
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static void ep93xx_gpio_irq_ack(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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ep93xx_gpio_update_int_params(port);
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}
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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gpio_int_unmasked[port] &= ~port_mask;
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ep93xx_gpio_update_int_params(port);
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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gpio_int_unmasked[port] &= ~(1 << (line & 7));
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ep93xx_gpio_update_int_params(port);
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}
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static void ep93xx_gpio_irq_unmask(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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gpio_int_unmasked[port] |= 1 << (line & 7);
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ep93xx_gpio_update_int_params(port);
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}
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/*
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* gpio_int_type1 controls whether the interrupt is level (0) or
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* edge (1) triggered, while gpio_int_type2 controls whether it
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* triggers on low/falling (0) or high/rising (1).
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*/
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static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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struct irq_desc *desc = irq_desc + irq;
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const int gpio = irq_to_gpio(irq);
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const int port = gpio >> 3;
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const int port_mask = 1 << (gpio & 7);
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gpio_direction_input(gpio);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] |= port_mask;
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desc->handle_irq = handle_edge_irq;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] &= ~port_mask;
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desc->handle_irq = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] |= port_mask;
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desc->handle_irq = handle_level_irq;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] &= ~port_mask;
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desc->handle_irq = handle_level_irq;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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gpio_int_type1[port] |= port_mask;
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/* set initial polarity based on current input level */
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if (gpio_get_value(gpio))
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gpio_int_type2[port] &= ~port_mask; /* falling */
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else
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gpio_int_type2[port] |= port_mask; /* rising */
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desc->handle_irq = handle_edge_irq;
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break;
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default:
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pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
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return -EINVAL;
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}
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gpio_int_enabled[port] |= port_mask;
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desc->status &= ~IRQ_TYPE_SENSE_MASK;
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desc->status |= type & IRQ_TYPE_SENSE_MASK;
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ep93xx_gpio_update_int_params(port);
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return 0;
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}
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static struct irq_chip ep93xx_gpio_irq_chip = {
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.name = "GPIO",
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.ack = ep93xx_gpio_irq_ack,
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.mask_ack = ep93xx_gpio_irq_mask_ack,
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.mask = ep93xx_gpio_irq_mask,
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.unmask = ep93xx_gpio_irq_unmask,
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.set_type = ep93xx_gpio_irq_type,
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};
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void __init ep93xx_gpio_init_irq(void)
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{
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int gpio_irq;
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for (gpio_irq = gpio_to_irq(0);
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gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
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set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
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set_irq_handler(gpio_irq, handle_level_irq);
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set_irq_flags(gpio_irq, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
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}
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/*************************************************************************
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* gpiolib interface for EP93xx on-chip GPIOs
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*************************************************************************/
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2008-04-16 03:56:35 +02:00
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struct ep93xx_gpio_chip {
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struct gpio_chip chip;
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2009-06-26 22:39:27 +02:00
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void __iomem *data_reg;
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void __iomem *data_dir_reg;
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2008-04-16 03:56:35 +02:00
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};
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#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
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static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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unsigned long flags;
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u8 v;
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local_irq_save(flags);
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v = __raw_readb(ep93xx_chip->data_dir_reg);
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v &= ~(1 << offset);
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__raw_writeb(v, ep93xx_chip->data_dir_reg);
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local_irq_restore(flags);
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return 0;
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}
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static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int val)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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unsigned long flags;
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int line;
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u8 v;
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local_irq_save(flags);
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/* Set the value */
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v = __raw_readb(ep93xx_chip->data_reg);
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if (val)
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v |= (1 << offset);
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else
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v &= ~(1 << offset);
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__raw_writeb(v, ep93xx_chip->data_reg);
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/* Drive as an output */
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line = chip->base + offset;
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if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
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/* Ports A/B/F */
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ep93xx_gpio_int_mask(line);
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ep93xx_gpio_update_int_params(line >> 3);
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}
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v = __raw_readb(ep93xx_chip->data_dir_reg);
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v |= (1 << offset);
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__raw_writeb(v, ep93xx_chip->data_dir_reg);
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local_irq_restore(flags);
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return 0;
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}
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static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
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}
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static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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unsigned long flags;
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u8 v;
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local_irq_save(flags);
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v = __raw_readb(ep93xx_chip->data_reg);
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if (val)
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v |= (1 << offset);
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else
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v &= ~(1 << offset);
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__raw_writeb(v, ep93xx_chip->data_reg);
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local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
|
|
|
{
|
|
|
|
struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
|
|
|
|
u8 data_reg, data_dir_reg;
|
2009-06-26 22:40:34 +02:00
|
|
|
int gpio, i;
|
2008-04-16 03:56:35 +02:00
|
|
|
|
|
|
|
data_reg = __raw_readb(ep93xx_chip->data_reg);
|
|
|
|
data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
|
|
|
|
|
2009-06-26 22:40:34 +02:00
|
|
|
gpio = ep93xx_chip->chip.base;
|
|
|
|
for (i = 0; i < chip->ngpio; i++, gpio++) {
|
|
|
|
int is_out = data_dir_reg & (1 << i);
|
|
|
|
|
|
|
|
seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s",
|
|
|
|
chip->label, i, gpio,
|
|
|
|
gpiochip_is_requested(chip, i) ? : "",
|
|
|
|
is_out ? "out" : "in ",
|
|
|
|
(data_reg & (1 << i)) ? "hi" : "lo");
|
|
|
|
|
|
|
|
if (!is_out) {
|
|
|
|
int irq = gpio_to_irq(gpio);
|
|
|
|
struct irq_desc *desc = irq_desc + irq;
|
|
|
|
|
|
|
|
if (irq >= 0 && desc->action) {
|
|
|
|
char *trigger;
|
|
|
|
|
|
|
|
switch (desc->status & IRQ_TYPE_SENSE_MASK) {
|
|
|
|
case IRQ_TYPE_NONE:
|
|
|
|
trigger = "(default)";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
|
|
trigger = "edge-falling";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
|
|
trigger = "edge-rising";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
|
|
trigger = "edge-both";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
|
|
trigger = "level-high";
|
|
|
|
break;
|
|
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
|
|
trigger = "level-low";
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
trigger = "?trigger?";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_printf(s, " irq-%d %s%s",
|
|
|
|
irq, trigger,
|
|
|
|
(desc->status & IRQ_WAKEUP)
|
|
|
|
? " wakeup" : "");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
seq_printf(s, "\n");
|
|
|
|
}
|
2008-04-16 03:56:35 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
|
|
|
|
{ \
|
|
|
|
.chip = { \
|
|
|
|
.label = name, \
|
|
|
|
.direction_input = ep93xx_gpio_direction_input, \
|
|
|
|
.direction_output = ep93xx_gpio_direction_output, \
|
|
|
|
.get = ep93xx_gpio_get, \
|
|
|
|
.set = ep93xx_gpio_set, \
|
|
|
|
.dbg_show = ep93xx_gpio_dbg_show, \
|
|
|
|
.base = base_gpio, \
|
|
|
|
.ngpio = 8, \
|
|
|
|
}, \
|
|
|
|
.data_reg = EP93XX_GPIO_REG(dr), \
|
|
|
|
.data_dir_reg = EP93XX_GPIO_REG(ddr), \
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
|
|
|
|
EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
|
|
|
|
EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
|
2008-09-05 18:24:40 +02:00
|
|
|
EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
|
2008-04-16 03:56:35 +02:00
|
|
|
EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
|
|
|
|
EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
|
2008-09-05 18:24:40 +02:00
|
|
|
EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
|
2008-04-16 03:56:35 +02:00
|
|
|
EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
|
|
|
|
EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
|
|
|
|
};
|
|
|
|
|
|
|
|
void __init ep93xx_gpio_init(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
|
|
|
|
gpiochip_add(&ep93xx_gpio_banks[i].chip);
|
|
|
|
}
|