300 lines
9.8 KiB
C
300 lines
9.8 KiB
C
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* Include file for Alchemy Semiconductor's Au1550 Descriptor
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* Based DMA Controller.
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*
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* Copyright 2004 Embedded Edge, LLC
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* dan@embeddededge.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
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* seen in the AU1550 part.
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*/
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#ifndef _AU1000_DBDMA_H_
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#define _AU1000_DBDMA_H_
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#include <linux/config.h>
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#ifndef _LANGUAGE_ASSEMBLY
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/* The DMA base addresses.
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* The Channels are every 256 bytes (0x0100) from the channel 0 base.
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* Interrupt status/enable is bits 15:0 for channels 15 to zero.
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*/
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#define DDMA_GLOBAL_BASE 0xb4003000
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#define DDMA_CHANNEL_BASE 0xb4002000
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typedef struct dbdma_global {
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u32 ddma_config;
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u32 ddma_intstat;
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u32 ddma_throttle;
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u32 ddma_inten;
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} dbdma_global_t;
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/* General Configuration.
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*/
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#define DDMA_CONFIG_AF (1 << 2)
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#define DDMA_CONFIG_AH (1 << 1)
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#define DDMA_CONFIG_AL (1 << 0)
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#define DDMA_THROTTLE_EN (1 << 31)
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/* The structure of a DMA Channel.
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*/
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typedef struct au1xxx_dma_channel {
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u32 ddma_cfg; /* See below */
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u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
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u32 ddma_statptr; /* word aligned pointer to status word */
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u32 ddma_dbell; /* A write activates channel operation */
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u32 ddma_irq; /* If bit 0 set, interrupt pending */
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u32 ddma_stat; /* See below */
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u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
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/* Remainder, up to the 256 byte boundary, is reserved.
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*/
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} au1x_dma_chan_t;
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#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
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#define DDMA_CFG_SP (1 << 8) /* source DMA polarity */
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#define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */
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#define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */
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#define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */
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#define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */
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#define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */
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#define DDMA_CFG_SBE (1 << 2) /* Source big endian */
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#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
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#define DDMA_CFG_EN (1 << 0) /* Channel enable */
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/* Always set when descriptor processing done, regardless of
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* interrupt enable state. Reflected in global intstat, don't
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* clear this until global intstat is read/used.
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*/
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#define DDMA_IRQ_IN (1 << 0)
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#define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */
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#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
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#define DDMA_STAT_H (1 << 0) /* Channel Halted */
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/* "Standard" DDMA Descriptor.
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* Must be 32-byte aligned.
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*/
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typedef struct au1xxx_ddma_desc {
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u32 dscr_cmd0; /* See below */
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u32 dscr_cmd1; /* See below */
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u32 dscr_source0; /* source phys address */
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u32 dscr_source1; /* See below */
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u32 dscr_dest0; /* Destination address */
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u32 dscr_dest1; /* See below */
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u32 dscr_stat; /* completion status */
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u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
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} au1x_ddma_desc_t;
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#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
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#define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */
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#define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
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#define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
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#define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
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#define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
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#define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
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#define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */
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#define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */
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#define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */
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#define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */
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#define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */
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#define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */
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#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
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#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
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/* Command 0 device IDs.
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*/
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#define DSCR_CMD0_UART0_TX 0
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#define DSCR_CMD0_UART0_RX 1
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#define DSCR_CMD0_UART3_TX 2
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#define DSCR_CMD0_UART3_RX 3
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#define DSCR_CMD0_DMA_REQ0 4
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#define DSCR_CMD0_DMA_REQ1 5
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#define DSCR_CMD0_DMA_REQ2 6
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#define DSCR_CMD0_DMA_REQ3 7
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#define DSCR_CMD0_USBDEV_RX0 8
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#define DSCR_CMD0_USBDEV_TX0 9
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#define DSCR_CMD0_USBDEV_TX1 10
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#define DSCR_CMD0_USBDEV_TX2 11
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#define DSCR_CMD0_USBDEV_RX3 12
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#define DSCR_CMD0_USBDEV_RX4 13
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#define DSCR_CMD0_PSC0_TX 14
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#define DSCR_CMD0_PSC0_RX 15
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#define DSCR_CMD0_PSC1_TX 16
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#define DSCR_CMD0_PSC1_RX 17
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#define DSCR_CMD0_PSC2_TX 18
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#define DSCR_CMD0_PSC2_RX 19
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#define DSCR_CMD0_PSC3_TX 20
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#define DSCR_CMD0_PSC3_RX 21
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#define DSCR_CMD0_PCI_WRITE 22
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#define DSCR_CMD0_NAND_FLASH 23
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#define DSCR_CMD0_MAC0_RX 24
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#define DSCR_CMD0_MAC0_TX 25
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#define DSCR_CMD0_MAC1_RX 26
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#define DSCR_CMD0_MAC1_TX 27
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#define DSCR_CMD0_THROTTLE 30
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#define DSCR_CMD0_ALWAYS 31
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#define DSCR_NDEV_IDS 32
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#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
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#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
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/* Source/Destination transfer width.
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*/
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#define DSCR_CMD0_BYTE 0
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#define DSCR_CMD0_HALFWORD 1
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#define DSCR_CMD0_WORD 2
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#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
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#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
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/* DDMA Descriptor Type.
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*/
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#define DSCR_CMD0_STANDARD 0
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#define DSCR_CMD0_LITERAL 1
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#define DSCR_CMD0_CMP_BRANCH 2
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#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
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/* Status Instruction.
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*/
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#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
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#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
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#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
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#define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */
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#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
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/* Descriptor Command 1
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*/
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#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
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#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
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#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
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#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
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/* Flag description.
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*/
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#define DSCR_CMD1_FL_MEM_STRIDE0 0
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#define DSCR_CMD1_FL_MEM_STRIDE1 1
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#define DSCR_CMD1_FL_MEM_STRIDE2 2
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#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
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/* Source1, 1-dimensional stride.
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*/
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#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
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#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
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#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
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#define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)
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#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
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#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
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/* Dest1, 1-dimensional stride.
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*/
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#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
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#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
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#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
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#define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)
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#define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */
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#define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)
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#define DSCR_xTS_SIZE1 0
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#define DSCR_xTS_SIZE2 1
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#define DSCR_xTS_SIZE4 2
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#define DSCR_xTS_SIZE8 3
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#define DSCR_SRC1_STS(x) (((x) & 3) << 30)
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#define DSCR_DEST1_DTS(x) (((x) & 3) << 30)
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#define DSCR_xAM_INCREMENT 0
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#define DSCR_xAM_DECREMENT 1
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#define DSCR_xAM_STATIC 2
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#define DSCR_xAM_BURST 3
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#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
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#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
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/* The next descriptor pointer.
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*/
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#define DSCR_NXTPTR_MASK (0x07ffffff)
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#define DSCR_NXTPTR(x) ((x) >> 5)
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#define DSCR_GET_NXTPTR(x) ((x) << 5)
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#define DSCR_NXTPTR_MS (1 << 27)
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/* The number of DBDMA channels.
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*/
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#define NUM_DBDMA_CHANS 16
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/* External functions for drivers to use.
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*/
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/* Use this to allocate a dbdma channel. The device ids are one of the
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* DSCR_CMD0 devices IDs, which is usually redefined to a more
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* meaningful name. The 'callback' is called during dma completion
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* interrupt.
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*/
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u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
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void (*callback)(int, void *, struct pt_regs *), void *callparam);
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#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
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/* ACK! These should be in a board specific description file.
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*/
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#ifdef CONFIG_MIPS_PB1550
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#endif
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#ifdef CONFIG_MIPS_DB1550
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#endif
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/* Set the device width of a in/out fifo.
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*/
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u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
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/* Allocate a ring of descriptors for dbdma.
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*/
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u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
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/* Put buffers on source/destination descriptors.
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*/
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u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
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u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
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/* Get a buffer from the destination descriptor.
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*/
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u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
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void au1xxx_dbdma_stop(u32 chanid);
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void au1xxx_dbdma_start(u32 chanid);
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void au1xxx_dbdma_reset(u32 chanid);
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u32 au1xxx_get_dma_residue(u32 chanid);
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void au1xxx_dbdma_chan_free(u32 chanid);
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void au1xxx_dbdma_dump(u32 chanid);
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#endif /* _LANGUAGE_ASSEMBLY */
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#endif /* _AU1000_DBDMA_H_ */
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