52 lines
1.7 KiB
C
52 lines
1.7 KiB
C
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/*
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* include/asm-sh/cpu-sh4/timer.h
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*
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* Copyright (C) 2004 Lineo Solutions, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_TIMER_H
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#define __ASM_CPU_SH4_TIMER_H
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/*
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* ---------------------------------------------------------------------------
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* TMU Common definitions for SH4 processors
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* SH7750S/SH7750R
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* SH7751/SH7751R
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* SH7760
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* ---------------------------------------------------------------------------
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*/
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#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
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#define TMU_TOCR 0xffd80000 /* Byte access */
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#endif
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#define TMU_TSTR 0xffd80004 /* Byte access */
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#define TMU0_TCOR 0xffd80008 /* Long access */
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#define TMU0_TCNT 0xffd8000c /* Long access */
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#define TMU0_TCR 0xffd80010 /* Word access */
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#define TMU1_TCOR 0xffd80014 /* Long access */
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#define TMU1_TCNT 0xffd80018 /* Long access */
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#define TMU1_TCR 0xffd8001c /* Word access */
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#define TMU2_TCOR 0xffd80020 /* Long access */
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#define TMU2_TCNT 0xffd80024 /* Long access */
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#define TMU2_TCR 0xffd80028 /* Word access */
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#define TMU2_TCPR 0xffd8002c /* Long access */
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#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
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#define TMU3_TCOR 0xfe100008 /* Long access */
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#define TMU3_TCNT 0xfe10000c /* Long access */
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#define TMU3_TCR 0xfe100010 /* Word access */
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#define TMU4_TCOR 0xfe100014 /* Long access */
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#define TMU4_TCNT 0xfe100018 /* Long access */
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#define TMU4_TCR 0xfe10001c /* Word access */
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#endif
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#endif /* __ASM_CPU_SH4_TIMER_H */
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