2005-11-10 15:26:51 +01:00
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/*
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2006-04-02 18:46:20 +02:00
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* linux/arch/arm/mach-omap2/prcm-reg.h
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*
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* OMAP24XX Power Reset and Clock Management (PRCM) registers
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2005-11-10 15:26:51 +01:00
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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2006-04-02 18:46:20 +02:00
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#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
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#define __ARCH_ARM_MACH_OMAP2_PRCM_H
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2005-11-10 15:26:51 +01:00
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/* SET_PERFORMANCE_LEVEL PARAMETERS */
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#define PRCM_HALF_SPEED 1
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#define PRCM_FULL_SPEED 2
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#ifndef __ASSEMBLER__
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#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
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#define PRCM_REVISION PRCM_REG32(0x000)
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#define PRCM_SYSCONFIG PRCM_REG32(0x010)
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#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
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#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
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#define PRCM_VOLTCTRL PRCM_REG32(0x050)
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#define PRCM_VOLTST PRCM_REG32(0x054)
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#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
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#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
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#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
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#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
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#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
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#define PRCM_VOLTSETUP PRCM_REG32(0x090)
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#define PRCM_CLKSSETUP PRCM_REG32(0x094)
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#define PRCM_POLCTRL PRCM_REG32(0x098)
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/* GENERAL PURPOSE */
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#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
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#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
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#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
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#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
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#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
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#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
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#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
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#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
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#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
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#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
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#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
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#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
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#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
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#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
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#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
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#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
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#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
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#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
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#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
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#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
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/* MPU */
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#define CM_CLKSEL_MPU PRCM_REG32(0x140)
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#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
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#define RM_RSTST_MPU PRCM_REG32(0x158)
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#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
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#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
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#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
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#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
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#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
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#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
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/* CORE */
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#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
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#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
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#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
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#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
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#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
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#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
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#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
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#define CM_IDLEST1_CORE PRCM_REG32(0x220)
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#define CM_IDLEST2_CORE PRCM_REG32(0x224)
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#define CM_IDLEST3_CORE PRCM_REG32(0x228)
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#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
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#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
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#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
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#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
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#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
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#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
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#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
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#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
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#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
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#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
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#define PM_WKST1_CORE PRCM_REG32(0x2B0)
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#define PM_WKST2_CORE PRCM_REG32(0x2B4)
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#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
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#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
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#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
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/* GFX */
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#define CM_FCLKEN_GFX PRCM_REG32(0x300)
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#define CM_ICLKEN_GFX PRCM_REG32(0x310)
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#define CM_IDLEST_GFX PRCM_REG32(0x320)
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#define CM_CLKSEL_GFX PRCM_REG32(0x340)
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#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
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#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
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#define RM_RSTST_GFX PRCM_REG32(0x358)
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#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
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#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
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#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
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/* WAKE-UP */
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#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
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#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
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#define CM_IDLEST_WKUP PRCM_REG32(0x420)
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#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
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#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
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#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
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#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
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#define RM_RSTST_WKUP PRCM_REG32(0x458)
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#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
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#define PM_WKST_WKUP PRCM_REG32(0x4B0)
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/* CLOCKS */
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#define CM_CLKEN_PLL PRCM_REG32(0x500)
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#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
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#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
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#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
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#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
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/* DSP */
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#define CM_FCLKEN_DSP PRCM_REG32(0x800)
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#define CM_ICLKEN_DSP PRCM_REG32(0x810)
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#define CM_IDLEST_DSP PRCM_REG32(0x820)
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#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
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#define CM_CLKSEL_DSP PRCM_REG32(0x840)
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#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
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#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
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#define RM_RSTST_DSP PRCM_REG32(0x858)
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#define PM_WKEN_DSP PRCM_REG32(0x8A0)
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#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
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#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
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#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
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#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
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#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
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/* IVA */
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#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
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#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
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/* Modem on 2430 */
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#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
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#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
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#define CM_IDLEST_MDM PRCM_REG32(0xC20)
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2006-04-02 18:46:20 +02:00
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#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
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2005-11-10 15:26:51 +01:00
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#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
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2006-04-02 18:46:20 +02:00
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#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
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#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
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#define RM_RSTST_MDM PRCM_REG32(0xC58)
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#define PM_WKEN_MDM PRCM_REG32(0xCA0)
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#define PM_WKST_MDM PRCM_REG32(0xCB0)
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#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
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#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
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#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
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#define OMAP24XX_L4_IO_BASE 0x48000000
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#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
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2005-11-10 15:26:51 +01:00
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#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
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2006-04-02 18:46:20 +02:00
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#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
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#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))
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2005-11-10 15:26:51 +01:00
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2006-04-02 18:46:20 +02:00
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/* FIXME: Move these to timer code */
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#define GPT1_BASE (0x48028000)
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2005-11-10 15:26:51 +01:00
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#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
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/* Misc sysconfig */
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#define DISPC_SYSCONFIG DISP_REG32(0x410)
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2006-04-02 18:46:20 +02:00
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#define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000)
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2005-11-10 15:26:51 +01:00
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#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
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2006-04-02 18:46:20 +02:00
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#define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10)
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#define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
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#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10)
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#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C)
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#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C)
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2005-11-10 15:26:51 +01:00
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#define GPMC_SYSCONFIG GPMC_REG32(0x010)
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2006-04-02 18:46:20 +02:00
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#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
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#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
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#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
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#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
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#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10)
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#define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000)
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#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10)
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#define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010)
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2005-11-10 15:26:51 +01:00
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/* rkw - good cannidates for PM_ to start what nm was trying */
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#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000)
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#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000)
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#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000)
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#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000)
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#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000)
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#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000)
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#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000)
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#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000)
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#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000)
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#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000)
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#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000)
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/* FIXME: Move these to timer code */
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2005-11-10 15:26:51 +01:00
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#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
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#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
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#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
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#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
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#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
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#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
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#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
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#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
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#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
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#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
|
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|
|
|
#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
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|
#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
|
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|
|
2006-04-02 18:46:20 +02:00
|
|
|
/* FIXME: Move these to gpio code */
|
|
|
|
|
#define OMAP24XX_GPIO_BASE 0x48018000
|
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|
|
|
#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
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|
|
#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10))
|
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|
|
#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10))
|
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|
|
#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10))
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|
|
#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10))
|
2005-11-10 15:26:51 +01:00
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|
2006-04-02 18:46:20 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP243X)
|
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|
#define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10))
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|
|
#endif
|
2005-11-10 15:26:51 +01:00
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|
|
/* GP TIMER 1 */
|
|
|
|
|
#define GPTIMER1_TISTAT GPT1_REG32(0x014)
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|
|
#define GPTIMER1_TISR GPT1_REG32(0x018)
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|
|
#define GPTIMER1_TIER GPT1_REG32(0x01C)
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|
|
#define GPTIMER1_TWER GPT1_REG32(0x020)
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|
|
#define GPTIMER1_TCLR GPT1_REG32(0x024)
|
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|
|
|
#define GPTIMER1_TCRR GPT1_REG32(0x028)
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|
|
#define GPTIMER1_TLDR GPT1_REG32(0x02C)
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|
|
#define GPTIMER1_TTGR GPT1_REG32(0x030)
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|
|
#define GPTIMER1_TWPS GPT1_REG32(0x034)
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|
|
#define GPTIMER1_TMAR GPT1_REG32(0x038)
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|
|
#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
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|
|
#define GPTIMER1_TSICR GPT1_REG32(0x040)
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|
|
#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
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|
|
/* rkw -- base fix up please... */
|
2006-04-02 18:46:20 +02:00
|
|
|
#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
|
2005-11-10 15:26:51 +01:00
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|
|
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|
|
/* SDRC */
|
2006-04-02 18:46:20 +02:00
|
|
|
#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
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|
|
|
#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
|
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|
|
|
#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
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|
|
|
#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
|
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|
|
|
#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
|
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|
|
|
#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
/* GPIO 1 */
|
|
|
|
|
#define GPIO1_BASE GPIOX_BASE(1)
|
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|
|
|
#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
|
|
|
|
|
#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
|
|
|
|
|
#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
|
|
|
|
|
#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
|
|
|
|
|
#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
|
|
|
|
|
#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
|
|
|
|
|
#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
|
|
|
|
|
#define GPIO1_DATAIN GPIO1_REG32(0x038)
|
|
|
|
|
#define GPIO1_OE GPIO1_REG32(0x034)
|
|
|
|
|
#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
|
|
|
|
|
|
|
|
|
|
/* GPIO2 */
|
|
|
|
|
#define GPIO2_BASE GPIOX_BASE(2)
|
|
|
|
|
#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
|
|
|
|
|
#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
|
|
|
|
|
#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
|
|
|
|
|
#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
|
|
|
|
|
#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
|
|
|
|
|
#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
|
|
|
|
|
#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
|
|
|
|
|
#define GPIO2_DATAIN GPIO2_REG32(0x038)
|
|
|
|
|
#define GPIO2_OE GPIO2_REG32(0x034)
|
|
|
|
|
#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
|
2006-04-02 18:46:20 +02:00
|
|
|
#define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050)
|
|
|
|
|
#define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054)
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
/* GPIO 3 */
|
|
|
|
|
#define GPIO3_BASE GPIOX_BASE(3)
|
|
|
|
|
#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
|
|
|
|
|
#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
|
|
|
|
|
#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
|
|
|
|
|
#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
|
|
|
|
|
#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
|
|
|
|
|
#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
|
|
|
|
|
#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
|
|
|
|
|
#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
|
|
|
|
|
#define GPIO3_DATAIN GPIO3_REG32(0x038)
|
|
|
|
|
#define GPIO3_OE GPIO3_REG32(0x034)
|
|
|
|
|
#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
|
|
|
|
|
#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
|
|
|
|
|
#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
|
2006-04-02 18:46:20 +02:00
|
|
|
#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
|
|
|
|
|
#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
/* GPIO 4 */
|
|
|
|
|
#define GPIO4_BASE GPIOX_BASE(4)
|
|
|
|
|
#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
|
|
|
|
|
#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
|
|
|
|
|
#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
|
|
|
|
|
#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
|
|
|
|
|
#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
|
|
|
|
|
#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
|
|
|
|
|
#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
|
|
|
|
|
#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
|
|
|
|
|
#define GPIO4_DATAIN GPIO4_REG32(0x038)
|
|
|
|
|
#define GPIO4_OE GPIO4_REG32(0x034)
|
|
|
|
|
#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
|
|
|
|
|
#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
|
|
|
|
|
#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
|
|
|
|
|
|
2006-04-02 18:46:20 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP243X)
|
|
|
|
|
/* GPIO 5 */
|
|
|
|
|
#define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset)))
|
|
|
|
|
#define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C)
|
|
|
|
|
#define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018)
|
|
|
|
|
#define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C)
|
|
|
|
|
#define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028)
|
|
|
|
|
#define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020)
|
|
|
|
|
#define GPIO5_RISINGDETECT GPIO5_REG32(0x048)
|
|
|
|
|
#define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C)
|
|
|
|
|
#define GPIO5_DATAIN GPIO5_REG32(0x038)
|
|
|
|
|
#define GPIO5_OE GPIO5_REG32(0x034)
|
|
|
|
|
#define GPIO5_DATAOUT GPIO5_REG32(0x03C)
|
|
|
|
|
#define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050)
|
|
|
|
|
#define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054)
|
|
|
|
|
#endif
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
/* IO CONFIG */
|
2006-04-02 18:46:20 +02:00
|
|
|
#define OMAP24XX_CTRL_BASE (L4_24XX_BASE)
|
|
|
|
|
#define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset))
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
|
|
|
|
|
#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
|
|
|
|
|
#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
|
|
|
|
|
#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
|
|
|
|
|
#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
|
|
|
|
|
#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
|
2006-04-02 18:46:20 +02:00
|
|
|
#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */
|
2005-11-10 15:26:51 +01:00
|
|
|
#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
|
|
|
|
|
#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
|
2006-04-02 18:46:20 +02:00
|
|
|
#define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */
|
|
|
|
|
#define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
/* CONTROL */
|
|
|
|
|
#define CONTROL_DEVCONF CONTROL_REG32(0x274)
|
2006-04-02 18:46:20 +02:00
|
|
|
#define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8)
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
/* INTERRUPT CONTROLLER */
|
2006-04-02 18:46:20 +02:00
|
|
|
#define INTC_BASE ((L4_24XX_BASE) + 0xfe000)
|
2005-11-10 15:26:51 +01:00
|
|
|
#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
|
|
|
|
|
|
|
|
|
|
#define INTC1_U_BASE INTC_REG32(0x000)
|
|
|
|
|
#define INTC_MIR0 INTC_REG32(0x084)
|
|
|
|
|
#define INTC_MIR_SET0 INTC_REG32(0x08C)
|
|
|
|
|
#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
|
|
|
|
|
#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
|
|
|
|
|
#define INTC_MIR1 INTC_REG32(0x0A4)
|
|
|
|
|
#define INTC_MIR_SET1 INTC_REG32(0x0AC)
|
|
|
|
|
#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
|
|
|
|
|
#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
|
|
|
|
|
#define INTC_MIR2 INTC_REG32(0x0C4)
|
|
|
|
|
#define INTC_MIR_SET2 INTC_REG32(0x0CC)
|
|
|
|
|
#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
|
|
|
|
|
#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
|
|
|
|
|
#define INTC_SIR_IRQ INTC_REG32(0x040)
|
|
|
|
|
#define INTC_CONTROL INTC_REG32(0x048)
|
2006-04-02 18:46:20 +02:00
|
|
|
#define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */
|
|
|
|
|
#define INTC_ILR30 INTC_REG32(0x178)
|
|
|
|
|
#define INTC_ILR31 INTC_REG32(0x17C)
|
2005-11-10 15:26:51 +01:00
|
|
|
#define INTC_ILR32 INTC_REG32(0x180)
|
2006-04-02 18:46:20 +02:00
|
|
|
#define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */
|
|
|
|
|
#define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */
|
2005-11-10 15:26:51 +01:00
|
|
|
|
|
|
|
|
/* RAM FIREWALL */
|
|
|
|
|
#define RAMFW_BASE (0x68005000)
|
|
|
|
|
#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
|
|
|
|
|
|
|
|
|
|
#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
|
|
|
|
|
#define RAMFW_READPERM0 RAMFW_REG32(0x050)
|
|
|
|
|
#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
|
|
|
|
|
|
|
|
|
|
/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
|
|
|
|
|
//#define DEBUG_BOARD_LED_REGISTER 0x04000014
|
|
|
|
|
|
|
|
|
|
/* GPMC CS0 */
|
|
|
|
|
#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
|
|
|
|
|
#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
|
|
|
|
|
#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
|
|
|
|
|
#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
|
|
|
|
|
#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
|
|
|
|
|
#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
|
|
|
|
|
#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
|
|
|
|
|
|
2006-04-02 18:46:20 +02:00
|
|
|
/* GPMC CS1 */
|
|
|
|
|
#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
|
|
|
|
|
#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
|
|
|
|
|
#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
|
|
|
|
|
#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
|
|
|
|
|
#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
|
|
|
|
|
#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
|
|
|
|
|
#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
|
|
|
|
|
|
|
|
|
|
/* GPMC CS3 */
|
|
|
|
|
#define GPMC_CONFIG1_3 GPMC_REG32(0x0F0)
|
|
|
|
|
#define GPMC_CONFIG2_3 GPMC_REG32(0x0F4)
|
|
|
|
|
#define GPMC_CONFIG3_3 GPMC_REG32(0x0F8)
|
|
|
|
|
#define GPMC_CONFIG4_3 GPMC_REG32(0x0FC)
|
|
|
|
|
#define GPMC_CONFIG5_3 GPMC_REG32(0x100)
|
|
|
|
|
#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
|
|
|
|
|
#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
|
|
|
|
|
|
2005-11-10 15:26:51 +01:00
|
|
|
/* DSS */
|
|
|
|
|
#define DSS_CONTROL DISP_REG32(0x040)
|
|
|
|
|
#define DISPC_CONTROL DISP_REG32(0x440)
|
|
|
|
|
#define DISPC_SYSSTATUS DISP_REG32(0x414)
|
|
|
|
|
#define DISPC_IRQSTATUS DISP_REG32(0x418)
|
|
|
|
|
#define DISPC_IRQENABLE DISP_REG32(0x41C)
|
|
|
|
|
#define DISPC_CONFIG DISP_REG32(0x444)
|
|
|
|
|
#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
|
|
|
|
|
#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
|
|
|
|
|
#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
|
|
|
|
|
#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
|
|
|
|
|
#define DISPC_LINE_NUMBER DISP_REG32(0x460)
|
|
|
|
|
#define DISPC_TIMING_H DISP_REG32(0x464)
|
|
|
|
|
#define DISPC_TIMING_V DISP_REG32(0x468)
|
|
|
|
|
#define DISPC_POL_FREQ DISP_REG32(0x46C)
|
|
|
|
|
#define DISPC_DIVISOR DISP_REG32(0x470)
|
|
|
|
|
#define DISPC_SIZE_DIG DISP_REG32(0x478)
|
|
|
|
|
#define DISPC_SIZE_LCD DISP_REG32(0x47C)
|
|
|
|
|
#define DISPC_GFX_BA0 DISP_REG32(0x480)
|
|
|
|
|
#define DISPC_GFX_BA1 DISP_REG32(0x484)
|
|
|
|
|
#define DISPC_GFX_POSITION DISP_REG32(0x488)
|
|
|
|
|
#define DISPC_GFX_SIZE DISP_REG32(0x48C)
|
|
|
|
|
#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
|
|
|
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#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
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#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
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#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
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#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
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#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
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#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
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#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
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#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
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2006-04-02 18:46:20 +02:00
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/* HSUSB Suspend */
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#define HSUSB_CTRL __REG8(0x480AC001)
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#define USBOTG_POWER __REG32(0x480AC000)
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/* HS MMC */
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#define MMCHS1_SYSCONFIG __REG32(0x4809C010)
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#define MMCHS2_SYSCONFIG __REG32(0x480b4010)
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2005-11-10 15:26:51 +01:00
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2006-04-02 18:46:20 +02:00
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#endif /* __ASSEMBLER__ */
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2005-11-10 15:26:51 +01:00
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#endif
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