android_kernel_motorola_sm6225/include/asm-blackfin/cplb.h

/************************************************************************
 *
 * cplb.h
 *
 * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
 *
 ************************************************************************/

/* Defines necessary for cplb initialisation routines. */

#ifndef _CPLB_H
#define _CPLB_H

# include <asm/blackfin.h>

#define CPLB_ENABLE_ICACHE_P	0
#define CPLB_ENABLE_DCACHE_P	1
#define CPLB_ENABLE_DCACHE2_P	2
#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
#define CPLB_ENABLE_ICPLBS_P	4
#define CPLB_ENABLE_DCPLBS_P	5

#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
				CPLB_ENABLE_ICPLBS | \
				CPLB_ENABLE_DCPLBS

#define CPLB_RELOADED		0x0000
#define CPLB_NO_UNLOCKED	0x0001
#define CPLB_NO_ADDR_MATCH	0x0002
#define CPLB_PROT_VIOL		0x0003
#define CPLB_UNKNOWN_ERR	0x0004

#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY

#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR

#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
#define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
#define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL

#endif				/* _CPLB_H */
blackfin architecture This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> 2007-05-06 23:50:22 +02:00			`/************************************************************************`
			`*`
			`* cplb.h`
			`*`
			`* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.`
			`*`
			`************************************************************************/`

			`/* Defines necessary for cplb initialisation routines. */`

			`#ifndef _CPLB_H`
			`#define _CPLB_H`

			`# include <asm/blackfin.h>`

			`#define CPLB_ENABLE_ICACHE_P 0`
			`#define CPLB_ENABLE_DCACHE_P 1`
			`#define CPLB_ENABLE_DCACHE2_P 2`
			`#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */`
			`#define CPLB_ENABLE_ICPLBS_P 4`
			`#define CPLB_ENABLE_DCPLBS_P 5`

			`#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)`
			`#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)`
			`#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)`
			`#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)`
			`#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)`
			`#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)`
			`#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS \| \`
			`CPLB_ENABLE_ICPLBS \| \`
			`CPLB_ENABLE_DCPLBS`

			`#define CPLB_RELOADED 0x0000`
			`#define CPLB_NO_UNLOCKED 0x0001`
			`#define CPLB_NO_ADDR_MATCH 0x0002`
			`#define CPLB_PROT_VIOL 0x0003`
			`#define CPLB_UNKNOWN_ERR 0x0004`

			`#define CPLB_DEF_CACHE CPLB_L1_CHBL \| CPLB_WT`
			`#define CPLB_CACHE_ENABLED CPLB_L1_CHBL \| CPLB_DIRTY`

			`#define CPLB_ALL_ACCESS CPLB_SUPV_WR \| CPLB_USER_RD \| CPLB_USER_WR`

			`#define CPLB_I_PAGE_MGMT CPLB_LOCK \| CPLB_VALID`
			`#define CPLB_D_PAGE_MGMT CPLB_LOCK \| CPLB_ALL_ACCESS \| CPLB_VALID`
			`#define CPLB_DNOCACHE CPLB_ALL_ACCESS \| CPLB_VALID`
			`#define CPLB_DDOCACHE CPLB_DNOCACHE \| CPLB_DEF_CACHE`
			`#define CPLB_INOCACHE CPLB_USER_RD \| CPLB_VALID`
			`#define CPLB_IDOCACHE CPLB_INOCACHE \| CPLB_L1_CHBL`

			`#endif /* _CPLB_H */`