2008-05-20 01:52:27 +02:00
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/*
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2005-04-17 00:20:36 +02:00
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* ultra.S: Don't expand these all over the place...
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*
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2008-05-20 08:46:00 +02:00
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* Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net)
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2005-04-17 00:20:36 +02:00
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*/
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#include <asm/asi.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/spitfire.h>
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#include <asm/mmu_context.h>
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2005-08-31 05:21:34 +02:00
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#include <asm/mmu.h>
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2005-04-17 00:20:36 +02:00
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#include <asm/pil.h>
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#include <asm/head.h>
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#include <asm/thread_info.h>
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#include <asm/cacheflush.h>
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2006-02-04 12:08:37 +01:00
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#include <asm/hypervisor.h>
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2008-05-20 08:46:00 +02:00
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#include <asm/cpudata.h>
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2005-04-17 00:20:36 +02:00
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/* Basically, most of the Spitfire vs. Cheetah madness
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* has to do with the fact that Cheetah does not support
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* IMMU flushes out of the secondary context. Someone needs
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* to throw a south lake birthday party for the folks
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* in Microelectronics who refused to fix this shit.
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*/
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/* This file is meant to be read efficiently by the CPU, not humans.
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* Staraj sie tego nikomu nie pierdolnac...
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*/
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.text
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.align 32
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.globl __flush_tlb_mm
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2006-02-04 12:08:37 +01:00
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__flush_tlb_mm: /* 18 insns */
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/* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
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2005-04-17 00:20:36 +02:00
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ldxa [%o1] ASI_DMMU, %g2
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cmp %g2, %o0
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bne,pn %icc, __spitfire_flush_tlb_mm_slow
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mov 0x50, %g3
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stxa %g0, [%g3] ASI_DMMU_DEMAP
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stxa %g0, [%g3] ASI_IMMU_DEMAP
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2006-02-01 03:33:00 +01:00
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sethi %hi(KERNBASE), %g3
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flush %g3
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2005-04-17 00:20:36 +02:00
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retl
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2006-02-01 03:33:00 +01:00
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nop
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2005-04-17 00:20:36 +02:00
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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2005-08-31 05:21:34 +02:00
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nop
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nop
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2005-04-17 00:20:36 +02:00
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.align 32
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.globl __flush_tlb_pending
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2006-02-04 12:08:37 +01:00
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__flush_tlb_pending: /* 26 insns */
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2005-04-17 00:20:36 +02:00
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/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
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rdpr %pstate, %g7
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sllx %o1, 3, %o1
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andn %g7, PSTATE_IE, %g2
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wrpr %g2, %pstate
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mov SECONDARY_CONTEXT, %o4
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ldxa [%o4] ASI_DMMU, %g2
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stxa %o0, [%o4] ASI_DMMU
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1: sub %o1, (1 << 3), %o1
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ldx [%o2 + %o1], %o3
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andcc %o3, 1, %g0
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andn %o3, 1, %o3
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be,pn %icc, 2f
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or %o3, 0x10, %o3
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stxa %g0, [%o3] ASI_IMMU_DEMAP
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2: stxa %g0, [%o3] ASI_DMMU_DEMAP
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membar #Sync
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brnz,pt %o1, 1b
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nop
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stxa %g2, [%o4] ASI_DMMU
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2006-02-01 03:33:00 +01:00
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sethi %hi(KERNBASE), %o4
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flush %o4
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2005-04-17 00:20:36 +02:00
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retl
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wrpr %g7, 0x0, %pstate
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2005-07-06 04:45:24 +02:00
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nop
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2005-08-31 05:21:34 +02:00
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nop
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nop
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nop
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2005-04-17 00:20:36 +02:00
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.align 32
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.globl __flush_tlb_kernel_range
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2006-02-16 05:35:10 +01:00
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__flush_tlb_kernel_range: /* 16 insns */
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2006-02-04 12:08:37 +01:00
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/* %o0=start, %o1=end */
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2005-04-17 00:20:36 +02:00
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cmp %o0, %o1
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be,pn %xcc, 2f
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sethi %hi(PAGE_SIZE), %o4
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sub %o1, %o0, %o3
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sub %o3, %o4, %o3
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or %o0, 0x20, %o0 ! Nucleus
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1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
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stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
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membar #Sync
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brnz,pt %o3, 1b
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sub %o3, %o4, %o3
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2006-02-01 03:33:00 +01:00
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2: sethi %hi(KERNBASE), %o3
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flush %o3
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retl
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nop
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2006-02-04 12:08:37 +01:00
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nop
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2005-04-17 00:20:36 +02:00
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__spitfire_flush_tlb_mm_slow:
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rdpr %pstate, %g1
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wrpr %g1, PSTATE_IE, %pstate
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stxa %o0, [%o1] ASI_DMMU
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stxa %g0, [%g3] ASI_DMMU_DEMAP
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stxa %g0, [%g3] ASI_IMMU_DEMAP
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flush %g6
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stxa %g2, [%o1] ASI_DMMU
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2006-02-01 03:33:00 +01:00
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sethi %hi(KERNBASE), %o1
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flush %o1
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2005-04-17 00:20:36 +02:00
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retl
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wrpr %g1, 0, %pstate
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/*
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* The following code flushes one page_size worth.
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*/
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2005-09-07 00:19:31 +02:00
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.section .kprobes.text, "ax"
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2005-04-17 00:20:36 +02:00
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.align 32
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.globl __flush_icache_page
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__flush_icache_page: /* %o0 = phys_page */
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srlx %o0, PAGE_SHIFT, %o0
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sethi %uhi(PAGE_OFFSET), %g1
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sllx %o0, PAGE_SHIFT, %o0
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sethi %hi(PAGE_SIZE), %g2
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sllx %g1, 32, %g1
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add %o0, %g1, %o0
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1: subcc %g2, 32, %g2
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bne,pt %icc, 1b
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flush %o0 + %g2
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retl
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nop
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#ifdef DCACHE_ALIASING_POSSIBLE
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#if (PAGE_SHIFT != 13)
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#error only page shift of 13 is supported by dcache flush
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#endif
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#define DTAG_MASK 0x3
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2005-09-27 01:06:03 +02:00
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/* This routine is Spitfire specific so the hardcoded
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* D-cache size and line-size are OK.
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*/
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2005-04-17 00:20:36 +02:00
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.align 64
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.globl __flush_dcache_page
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__flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
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sethi %uhi(PAGE_OFFSET), %g1
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sllx %g1, 32, %g1
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2005-09-27 01:06:03 +02:00
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sub %o0, %g1, %o0 ! physical address
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srlx %o0, 11, %o0 ! make D-cache TAG
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sethi %hi(1 << 14), %o2 ! D-cache size
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sub %o2, (1 << 5), %o2 ! D-cache line size
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1: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG
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andcc %o3, DTAG_MASK, %g0 ! Valid?
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be,pn %xcc, 2f ! Nope, branch
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andn %o3, DTAG_MASK, %o3 ! Clear valid bits
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cmp %o3, %o0 ! TAG match?
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bne,pt %xcc, 2f ! Nope, branch
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nop
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stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG
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membar #Sync
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2: brnz,pt %o2, 1b
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sub %o2, (1 << 5), %o2 ! D-cache line size
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2005-04-17 00:20:36 +02:00
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/* The I-cache does not snoop local stores so we
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* better flush that too when necessary.
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*/
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brnz,pt %o1, __flush_icache_page
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sllx %o0, 11, %o0
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retl
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nop
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#endif /* DCACHE_ALIASING_POSSIBLE */
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2005-09-27 01:06:03 +02:00
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.previous
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2005-08-31 05:21:34 +02:00
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/* Cheetah specific versions, patched at boot time. */
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2006-02-01 03:33:00 +01:00
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__cheetah_flush_tlb_mm: /* 19 insns */
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2005-04-17 00:20:36 +02:00
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rdpr %pstate, %g7
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andn %g7, PSTATE_IE, %g2
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wrpr %g2, 0x0, %pstate
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wrpr %g0, 1, %tl
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mov PRIMARY_CONTEXT, %o2
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mov 0x40, %g3
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ldxa [%o2] ASI_DMMU, %g2
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2005-08-31 05:21:34 +02:00
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srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1
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sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1
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or %o0, %o1, %o0 /* Preserve nucleus page size fields */
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2005-04-17 00:20:36 +02:00
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stxa %o0, [%o2] ASI_DMMU
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stxa %g0, [%g3] ASI_DMMU_DEMAP
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stxa %g0, [%g3] ASI_IMMU_DEMAP
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stxa %g2, [%o2] ASI_DMMU
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2006-02-01 03:33:00 +01:00
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sethi %hi(KERNBASE), %o2
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flush %o2
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2005-04-17 00:20:36 +02:00
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wrpr %g0, 0, %tl
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retl
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wrpr %g7, 0x0, %pstate
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2006-02-01 03:33:00 +01:00
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__cheetah_flush_tlb_pending: /* 27 insns */
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2005-04-17 00:20:36 +02:00
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/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
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rdpr %pstate, %g7
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sllx %o1, 3, %o1
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andn %g7, PSTATE_IE, %g2
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wrpr %g2, 0x0, %pstate
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wrpr %g0, 1, %tl
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mov PRIMARY_CONTEXT, %o4
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ldxa [%o4] ASI_DMMU, %g2
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2005-08-31 05:21:34 +02:00
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srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
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sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
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or %o0, %o3, %o0 /* Preserve nucleus page size fields */
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2005-04-17 00:20:36 +02:00
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stxa %o0, [%o4] ASI_DMMU
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1: sub %o1, (1 << 3), %o1
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ldx [%o2 + %o1], %o3
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andcc %o3, 1, %g0
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be,pn %icc, 2f
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andn %o3, 1, %o3
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stxa %g0, [%o3] ASI_IMMU_DEMAP
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2: stxa %g0, [%o3] ASI_DMMU_DEMAP
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 00:42:04 +02:00
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membar #Sync
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2005-04-17 00:20:36 +02:00
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brnz,pt %o1, 1b
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 00:42:04 +02:00
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nop
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2005-04-17 00:20:36 +02:00
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stxa %g2, [%o4] ASI_DMMU
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2006-02-01 03:33:00 +01:00
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sethi %hi(KERNBASE), %o4
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flush %o4
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2005-04-17 00:20:36 +02:00
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wrpr %g0, 0, %tl
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retl
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wrpr %g7, 0x0, %pstate
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#ifdef DCACHE_ALIASING_POSSIBLE
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2005-09-27 01:06:03 +02:00
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__cheetah_flush_dcache_page: /* 11 insns */
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2005-04-17 00:20:36 +02:00
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sethi %uhi(PAGE_OFFSET), %g1
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sllx %g1, 32, %g1
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sub %o0, %g1, %o0
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sethi %hi(PAGE_SIZE), %o4
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1: subcc %o4, (1 << 5), %o4
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stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
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membar #Sync
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bne,pt %icc, 1b
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nop
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retl /* I-cache flush never needed on Cheetah, see callers. */
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nop
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#endif /* DCACHE_ALIASING_POSSIBLE */
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2006-02-04 12:08:37 +01:00
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/* Hypervisor specific versions, patched at boot time. */
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2006-02-27 04:31:49 +01:00
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__hypervisor_tlb_tl0_error:
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save %sp, -192, %sp
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mov %i0, %o0
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call hypervisor_tlbop_error
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mov %i1, %o1
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ret
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restore
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__hypervisor_flush_tlb_mm: /* 10 insns */
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2006-02-04 12:08:37 +01:00
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mov %o0, %o2 /* ARG2: mmu context */
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mov 0, %o0 /* ARG0: CPU lists unimplemented */
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mov 0, %o1 /* ARG1: CPU lists unimplemented */
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mov HV_MMU_ALL, %o3 /* ARG3: flags */
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mov HV_FAST_MMU_DEMAP_CTX, %o5
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ta HV_FAST_TRAP
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2006-02-27 04:31:49 +01:00
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brnz,pn %o0, __hypervisor_tlb_tl0_error
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mov HV_FAST_MMU_DEMAP_CTX, %o1
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2006-02-04 12:08:37 +01:00
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retl
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nop
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2006-02-27 04:31:49 +01:00
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__hypervisor_flush_tlb_pending: /* 16 insns */
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2006-02-04 12:08:37 +01:00
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/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
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sllx %o1, 3, %g1
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mov %o2, %g2
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mov %o0, %g3
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1: sub %g1, (1 << 3), %g1
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|
|
ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit */
|
|
|
|
mov %g3, %o1 /* ARG1: mmu context */
|
2006-02-27 04:31:49 +01:00
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
srlx %o0, PAGE_SHIFT, %o0
|
|
|
|
sllx %o0, PAGE_SHIFT, %o0
|
2006-02-04 12:08:37 +01:00
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2006-02-27 04:31:49 +01:00
|
|
|
brnz,pn %o0, __hypervisor_tlb_tl0_error
|
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %o1
|
2006-02-04 12:08:37 +01:00
|
|
|
brnz,pt %g1, 1b
|
|
|
|
nop
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
|
2006-02-27 04:31:49 +01:00
|
|
|
__hypervisor_flush_tlb_kernel_range: /* 16 insns */
|
2006-02-04 12:08:37 +01:00
|
|
|
/* %o0=start, %o1=end */
|
|
|
|
cmp %o0, %o1
|
|
|
|
be,pn %xcc, 2f
|
|
|
|
sethi %hi(PAGE_SIZE), %g3
|
|
|
|
mov %o0, %g1
|
|
|
|
sub %o1, %g1, %g2
|
|
|
|
sub %g2, %g3, %g2
|
|
|
|
1: add %g1, %g2, %o0 /* ARG0: virtual address */
|
|
|
|
mov 0, %o1 /* ARG1: mmu context */
|
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2006-02-27 04:31:49 +01:00
|
|
|
brnz,pn %o0, __hypervisor_tlb_tl0_error
|
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %o1
|
2006-02-04 12:08:37 +01:00
|
|
|
brnz,pt %g2, 1b
|
|
|
|
sub %g2, %g3, %g2
|
|
|
|
2: retl
|
|
|
|
nop
|
|
|
|
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
/* XXX Niagara and friends have an 8K cache, so no aliasing is
|
|
|
|
* XXX possible, but nothing explicit in the Hypervisor API
|
|
|
|
* XXX guarantees this.
|
|
|
|
*/
|
|
|
|
__hypervisor_flush_dcache_page: /* 2 insns */
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
#endif
|
|
|
|
|
|
|
|
tlb_patch_one:
|
2005-04-17 00:20:36 +02:00
|
|
|
1: lduw [%o1], %g1
|
|
|
|
stw %g1, [%o0]
|
|
|
|
flush %o0
|
|
|
|
subcc %o2, 1, %o2
|
|
|
|
add %o1, 4, %o1
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
add %o0, 4, %o0
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
|
|
|
|
.globl cheetah_patch_cachetlbops
|
|
|
|
cheetah_patch_cachetlbops:
|
|
|
|
save %sp, -128, %sp
|
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_mm), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_mm), %o0
|
|
|
|
sethi %hi(__cheetah_flush_tlb_mm), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_tlb_mm), %o1
|
2006-02-04 12:08:37 +01:00
|
|
|
call tlb_patch_one
|
2006-02-01 03:33:00 +01:00
|
|
|
mov 19, %o2
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_pending), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_pending), %o0
|
|
|
|
sethi %hi(__cheetah_flush_tlb_pending), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_tlb_pending), %o1
|
2006-02-04 12:08:37 +01:00
|
|
|
call tlb_patch_one
|
2006-02-01 03:33:00 +01:00
|
|
|
mov 27, %o2
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
sethi %hi(__flush_dcache_page), %o0
|
|
|
|
or %o0, %lo(__flush_dcache_page), %o0
|
2005-09-27 01:06:03 +02:00
|
|
|
sethi %hi(__cheetah_flush_dcache_page), %o1
|
|
|
|
or %o1, %lo(__cheetah_flush_dcache_page), %o1
|
2006-02-04 12:08:37 +01:00
|
|
|
call tlb_patch_one
|
2005-04-17 00:20:36 +02:00
|
|
|
mov 11, %o2
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
|
|
|
ret
|
|
|
|
restore
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
/* These are all called by the slaves of a cross call, at
|
|
|
|
* trap level 1, with interrupts fully disabled.
|
|
|
|
*
|
|
|
|
* Register usage:
|
|
|
|
* %g5 mm->context (all tlb flushes)
|
|
|
|
* %g1 address arg 1 (tlb page and range flushes)
|
|
|
|
* %g7 address arg 2 (tlb range flush only)
|
|
|
|
*
|
2006-02-27 08:24:22 +01:00
|
|
|
* %g6 scratch 1
|
|
|
|
* %g2 scratch 2
|
|
|
|
* %g3 scratch 3
|
|
|
|
* %g4 scratch 4
|
2005-04-17 00:20:36 +02:00
|
|
|
*/
|
|
|
|
.align 32
|
|
|
|
.globl xcall_flush_tlb_mm
|
2006-02-27 04:31:49 +01:00
|
|
|
xcall_flush_tlb_mm: /* 21 insns */
|
2005-04-17 00:20:36 +02:00
|
|
|
mov PRIMARY_CONTEXT, %g2
|
|
|
|
ldxa [%g2] ASI_DMMU, %g3
|
2005-08-31 05:21:34 +02:00
|
|
|
srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
or %g5, %g4, %g5 /* Preserve nucleus page size fields */
|
2005-04-17 00:20:36 +02:00
|
|
|
stxa %g5, [%g2] ASI_DMMU
|
2005-08-31 05:21:34 +02:00
|
|
|
mov 0x40, %g4
|
2005-04-17 00:20:36 +02:00
|
|
|
stxa %g0, [%g4] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%g4] ASI_IMMU_DEMAP
|
|
|
|
stxa %g3, [%g2] ASI_DMMU
|
|
|
|
retry
|
2006-02-04 12:08:37 +01:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2006-02-27 04:31:49 +01:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
.globl xcall_flush_tlb_pending
|
2006-02-27 04:31:49 +01:00
|
|
|
xcall_flush_tlb_pending: /* 21 insns */
|
2005-04-17 00:20:36 +02:00
|
|
|
/* %g5=context, %g1=nr, %g7=vaddrs[] */
|
|
|
|
sllx %g1, 3, %g1
|
|
|
|
mov PRIMARY_CONTEXT, %g4
|
|
|
|
ldxa [%g4] ASI_DMMU, %g2
|
2005-08-31 05:21:34 +02:00
|
|
|
srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
|
|
|
|
or %g5, %g4, %g5
|
|
|
|
mov PRIMARY_CONTEXT, %g4
|
2005-04-17 00:20:36 +02:00
|
|
|
stxa %g5, [%g4] ASI_DMMU
|
|
|
|
1: sub %g1, (1 << 3), %g1
|
|
|
|
ldx [%g7 + %g1], %g5
|
|
|
|
andcc %g5, 0x1, %g0
|
|
|
|
be,pn %icc, 2f
|
|
|
|
|
|
|
|
andn %g5, 0x1, %g5
|
|
|
|
stxa %g0, [%g5] ASI_IMMU_DEMAP
|
|
|
|
2: stxa %g0, [%g5] ASI_DMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
brnz,pt %g1, 1b
|
|
|
|
nop
|
|
|
|
stxa %g2, [%g4] ASI_DMMU
|
|
|
|
retry
|
2006-02-27 04:31:49 +01:00
|
|
|
nop
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
.globl xcall_flush_tlb_kernel_range
|
2006-02-27 04:31:49 +01:00
|
|
|
xcall_flush_tlb_kernel_range: /* 25 insns */
|
2005-04-17 00:20:36 +02:00
|
|
|
sethi %hi(PAGE_SIZE - 1), %g2
|
|
|
|
or %g2, %lo(PAGE_SIZE - 1), %g2
|
|
|
|
andn %g1, %g2, %g1
|
|
|
|
andn %g7, %g2, %g7
|
|
|
|
sub %g7, %g1, %g3
|
|
|
|
add %g2, 1, %g2
|
|
|
|
sub %g3, %g2, %g3
|
|
|
|
or %g1, 0x20, %g1 ! Nucleus
|
|
|
|
1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
|
|
|
|
stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
|
|
|
|
membar #Sync
|
|
|
|
brnz,pt %g3, 1b
|
|
|
|
sub %g3, %g2, %g3
|
|
|
|
retry
|
|
|
|
nop
|
|
|
|
nop
|
2006-02-04 12:08:37 +01:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2006-02-27 04:31:49 +01:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2005-04-17 00:20:36 +02:00
|
|
|
|
|
|
|
/* This runs in a very controlled environment, so we do
|
|
|
|
* not need to worry about BH races etc.
|
|
|
|
*/
|
|
|
|
.globl xcall_sync_tick
|
|
|
|
xcall_sync_tick:
|
2006-02-06 07:27:28 +01:00
|
|
|
|
|
|
|
661: rdpr %pstate, %g2
|
2005-04-17 00:20:36 +02:00
|
|
|
wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
|
2006-02-07 09:00:16 +01:00
|
|
|
.section .sun4v_2insn_patch, "ax"
|
2006-02-06 07:27:28 +01:00
|
|
|
.word 661b
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
.previous
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
rdpr %pil, %g2
|
2008-11-24 06:55:29 +01:00
|
|
|
wrpr %g0, PIL_NORMAL_MAX, %pil
|
2005-04-17 00:20:36 +02:00
|
|
|
sethi %hi(109f), %g7
|
|
|
|
b,pt %xcc, etrap_irq
|
|
|
|
109: or %g7, %lo(109b), %g7
|
2006-11-16 22:38:57 +01:00
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
|
|
call trace_hardirqs_off
|
|
|
|
nop
|
|
|
|
#endif
|
2005-04-17 00:20:36 +02:00
|
|
|
call smp_synchronize_tick_client
|
|
|
|
nop
|
|
|
|
b rtrap_xcall
|
|
|
|
ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
|
|
|
|
|
2008-05-20 08:46:00 +02:00
|
|
|
.globl xcall_fetch_glob_regs
|
|
|
|
xcall_fetch_glob_regs:
|
|
|
|
sethi %hi(global_reg_snapshot), %g1
|
|
|
|
or %g1, %lo(global_reg_snapshot), %g1
|
|
|
|
__GET_CPUID(%g2)
|
|
|
|
sllx %g2, 6, %g3
|
|
|
|
add %g1, %g3, %g1
|
|
|
|
rdpr %tstate, %g7
|
|
|
|
stx %g7, [%g1 + GR_SNAP_TSTATE]
|
|
|
|
rdpr %tpc, %g7
|
|
|
|
stx %g7, [%g1 + GR_SNAP_TPC]
|
|
|
|
rdpr %tnpc, %g7
|
|
|
|
stx %g7, [%g1 + GR_SNAP_TNPC]
|
|
|
|
stx %o7, [%g1 + GR_SNAP_O7]
|
|
|
|
stx %i7, [%g1 + GR_SNAP_I7]
|
2008-07-31 06:57:59 +02:00
|
|
|
/* Don't try this at home kids... */
|
|
|
|
rdpr %cwp, %g2
|
|
|
|
sub %g2, 1, %g7
|
|
|
|
wrpr %g7, %cwp
|
|
|
|
mov %i7, %g7
|
|
|
|
wrpr %g2, %cwp
|
|
|
|
stx %g7, [%g1 + GR_SNAP_RPC]
|
2008-05-20 08:46:00 +02:00
|
|
|
sethi %hi(trap_block), %g7
|
|
|
|
or %g7, %lo(trap_block), %g7
|
|
|
|
sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
|
|
|
|
add %g7, %g2, %g7
|
|
|
|
ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
|
|
|
|
stx %g3, [%g1 + GR_SNAP_THREAD]
|
|
|
|
retry
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
.align 32
|
|
|
|
.globl xcall_flush_dcache_page_cheetah
|
|
|
|
xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
|
|
|
|
sethi %hi(PAGE_SIZE), %g3
|
|
|
|
1: subcc %g3, (1 << 5), %g3
|
|
|
|
stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
|
|
|
|
membar #Sync
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
nop
|
|
|
|
retry
|
|
|
|
nop
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
|
|
|
.globl xcall_flush_dcache_page_spitfire
|
|
|
|
xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
|
|
|
|
%g7 == kernel page virtual address
|
|
|
|
%g5 == (page->mapping != NULL) */
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
srlx %g1, (13 - 2), %g1 ! Form tag comparitor
|
|
|
|
sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
|
|
|
|
sub %g3, (1 << 5), %g3 ! D$ linesize == 32
|
|
|
|
1: ldxa [%g3] ASI_DCACHE_TAG, %g2
|
|
|
|
andcc %g2, 0x3, %g0
|
|
|
|
be,pn %xcc, 2f
|
|
|
|
andn %g2, 0x3, %g2
|
|
|
|
cmp %g2, %g1
|
|
|
|
|
|
|
|
bne,pt %xcc, 2f
|
|
|
|
nop
|
|
|
|
stxa %g0, [%g3] ASI_DCACHE_TAG
|
|
|
|
membar #Sync
|
|
|
|
2: cmp %g3, 0
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
sub %g3, (1 << 5), %g3
|
|
|
|
|
|
|
|
brz,pn %g5, 2f
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
sethi %hi(PAGE_SIZE), %g3
|
|
|
|
|
|
|
|
1: flush %g7
|
|
|
|
subcc %g3, (1 << 5), %g3
|
|
|
|
bne,pt %icc, 1b
|
|
|
|
add %g7, (1 << 5), %g7
|
|
|
|
|
|
|
|
2: retry
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
|
2006-02-27 04:31:49 +01:00
|
|
|
/* %g5: error
|
|
|
|
* %g6: tlb op
|
|
|
|
*/
|
|
|
|
__hypervisor_tlb_xcall_error:
|
|
|
|
mov %g5, %g4
|
|
|
|
mov %g6, %g5
|
|
|
|
ba,pt %xcc, etrap
|
|
|
|
rd %pc, %g7
|
|
|
|
mov %l4, %o0
|
|
|
|
call hypervisor_tlbop_error_xcall
|
|
|
|
mov %l5, %o1
|
2008-04-24 12:15:22 +02:00
|
|
|
ba,a,pt %xcc, rtrap
|
2006-02-27 04:31:49 +01:00
|
|
|
|
2006-02-04 12:08:37 +01:00
|
|
|
.globl __hypervisor_xcall_flush_tlb_mm
|
2006-02-27 04:31:49 +01:00
|
|
|
__hypervisor_xcall_flush_tlb_mm: /* 21 insns */
|
2006-02-04 12:08:37 +01:00
|
|
|
/* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */
|
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %g3
|
|
|
|
mov %o2, %g4
|
|
|
|
mov %o3, %g1
|
|
|
|
mov %o5, %g7
|
|
|
|
clr %o0 /* ARG0: CPU lists unimplemented */
|
|
|
|
clr %o1 /* ARG1: CPU lists unimplemented */
|
|
|
|
mov %g5, %o2 /* ARG2: mmu context */
|
|
|
|
mov HV_MMU_ALL, %o3 /* ARG3: flags */
|
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %o5
|
|
|
|
ta HV_FAST_TRAP
|
2006-02-27 04:31:49 +01:00
|
|
|
mov HV_FAST_MMU_DEMAP_CTX, %g6
|
|
|
|
brnz,pn %o0, __hypervisor_tlb_xcall_error
|
|
|
|
mov %o0, %g5
|
2006-02-04 12:08:37 +01:00
|
|
|
mov %g2, %o0
|
|
|
|
mov %g3, %o1
|
|
|
|
mov %g4, %o2
|
|
|
|
mov %g1, %o3
|
|
|
|
mov %g7, %o5
|
|
|
|
membar #Sync
|
|
|
|
retry
|
|
|
|
|
|
|
|
.globl __hypervisor_xcall_flush_tlb_pending
|
2006-02-27 04:31:49 +01:00
|
|
|
__hypervisor_xcall_flush_tlb_pending: /* 21 insns */
|
|
|
|
/* %g5=ctx, %g1=nr, %g7=vaddrs[], %g2,%g3,%g4,g6=scratch */
|
2006-02-04 12:08:37 +01:00
|
|
|
sllx %g1, 3, %g1
|
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %g3
|
|
|
|
mov %o2, %g4
|
|
|
|
1: sub %g1, (1 << 3), %g1
|
|
|
|
ldx [%g7 + %g1], %o0 /* ARG0: virtual address */
|
|
|
|
mov %g5, %o1 /* ARG1: mmu context */
|
2006-02-27 04:31:49 +01:00
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
srlx %o0, PAGE_SHIFT, %o0
|
|
|
|
sllx %o0, PAGE_SHIFT, %o0
|
2006-02-04 12:08:37 +01:00
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2006-02-27 04:31:49 +01:00
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %g6
|
|
|
|
brnz,a,pn %o0, __hypervisor_tlb_xcall_error
|
|
|
|
mov %o0, %g5
|
2006-02-04 12:08:37 +01:00
|
|
|
brnz,pt %g1, 1b
|
|
|
|
nop
|
|
|
|
mov %g2, %o0
|
|
|
|
mov %g3, %o1
|
|
|
|
mov %g4, %o2
|
|
|
|
membar #Sync
|
|
|
|
retry
|
|
|
|
|
|
|
|
.globl __hypervisor_xcall_flush_tlb_kernel_range
|
2006-02-27 04:31:49 +01:00
|
|
|
__hypervisor_xcall_flush_tlb_kernel_range: /* 25 insns */
|
|
|
|
/* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */
|
2006-02-04 12:08:37 +01:00
|
|
|
sethi %hi(PAGE_SIZE - 1), %g2
|
|
|
|
or %g2, %lo(PAGE_SIZE - 1), %g2
|
|
|
|
andn %g1, %g2, %g1
|
|
|
|
andn %g7, %g2, %g7
|
|
|
|
sub %g7, %g1, %g3
|
|
|
|
add %g2, 1, %g2
|
|
|
|
sub %g3, %g2, %g3
|
|
|
|
mov %o0, %g2
|
|
|
|
mov %o1, %g4
|
2006-02-27 04:31:49 +01:00
|
|
|
mov %o2, %g7
|
2006-02-04 12:08:37 +01:00
|
|
|
1: add %g1, %g3, %o0 /* ARG0: virtual address */
|
|
|
|
mov 0, %o1 /* ARG1: mmu context */
|
|
|
|
mov HV_MMU_ALL, %o2 /* ARG2: flags */
|
|
|
|
ta HV_MMU_UNMAP_ADDR_TRAP
|
2006-02-27 04:31:49 +01:00
|
|
|
mov HV_MMU_UNMAP_ADDR_TRAP, %g6
|
|
|
|
brnz,pn %o0, __hypervisor_tlb_xcall_error
|
|
|
|
mov %o0, %g5
|
2006-02-04 12:08:37 +01:00
|
|
|
sethi %hi(PAGE_SIZE), %o2
|
|
|
|
brnz,pt %g3, 1b
|
|
|
|
sub %g3, %o2, %g3
|
|
|
|
mov %g2, %o0
|
|
|
|
mov %g4, %o1
|
2006-02-27 04:31:49 +01:00
|
|
|
mov %g7, %o2
|
2006-02-04 12:08:37 +01:00
|
|
|
membar #Sync
|
|
|
|
retry
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
/* These just get rescheduled to PIL vectors. */
|
|
|
|
.globl xcall_call_function
|
|
|
|
xcall_call_function:
|
|
|
|
wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
|
|
|
|
retry
|
|
|
|
|
2008-07-18 08:44:50 +02:00
|
|
|
.globl xcall_call_function_single
|
|
|
|
xcall_call_function_single:
|
|
|
|
wr %g0, (1 << PIL_SMP_CALL_FUNC_SNGL), %set_softint
|
|
|
|
retry
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
.globl xcall_receive_signal
|
|
|
|
xcall_receive_signal:
|
|
|
|
wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
|
|
|
|
retry
|
|
|
|
|
|
|
|
.globl xcall_capture
|
|
|
|
xcall_capture:
|
|
|
|
wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
|
|
|
|
retry
|
|
|
|
|
2006-03-07 07:50:44 +01:00
|
|
|
.globl xcall_new_mmu_context_version
|
|
|
|
xcall_new_mmu_context_version:
|
|
|
|
wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint
|
|
|
|
retry
|
|
|
|
|
2008-04-29 11:38:50 +02:00
|
|
|
#ifdef CONFIG_KGDB
|
|
|
|
.globl xcall_kgdb_capture
|
|
|
|
xcall_kgdb_capture:
|
2009-03-19 07:51:57 +01:00
|
|
|
wr %g0, (1 << PIL_KGDB_CAPTURE), %set_softint
|
|
|
|
retry
|
2008-04-29 11:38:50 +02:00
|
|
|
#endif
|
|
|
|
|
2005-04-17 00:20:36 +02:00
|
|
|
#endif /* CONFIG_SMP */
|
2006-02-04 12:08:37 +01:00
|
|
|
|
|
|
|
|
|
|
|
.globl hypervisor_patch_cachetlbops
|
|
|
|
hypervisor_patch_cachetlbops:
|
|
|
|
save %sp, -128, %sp
|
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_mm), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_mm), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_tlb_mm), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_tlb_mm), %o1
|
|
|
|
call tlb_patch_one
|
2006-02-27 04:31:49 +01:00
|
|
|
mov 10, %o2
|
2006-02-04 12:08:37 +01:00
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_pending), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_pending), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_tlb_pending), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_tlb_pending), %o1
|
|
|
|
call tlb_patch_one
|
2006-02-27 04:31:49 +01:00
|
|
|
mov 16, %o2
|
2006-02-04 12:08:37 +01:00
|
|
|
|
|
|
|
sethi %hi(__flush_tlb_kernel_range), %o0
|
|
|
|
or %o0, %lo(__flush_tlb_kernel_range), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_tlb_kernel_range), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_tlb_kernel_range), %o1
|
|
|
|
call tlb_patch_one
|
2006-02-27 04:31:49 +01:00
|
|
|
mov 16, %o2
|
2006-02-04 12:08:37 +01:00
|
|
|
|
|
|
|
#ifdef DCACHE_ALIASING_POSSIBLE
|
|
|
|
sethi %hi(__flush_dcache_page), %o0
|
|
|
|
or %o0, %lo(__flush_dcache_page), %o0
|
|
|
|
sethi %hi(__hypervisor_flush_dcache_page), %o1
|
|
|
|
or %o1, %lo(__hypervisor_flush_dcache_page), %o1
|
|
|
|
call tlb_patch_one
|
|
|
|
mov 2, %o2
|
|
|
|
#endif /* DCACHE_ALIASING_POSSIBLE */
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
sethi %hi(xcall_flush_tlb_mm), %o0
|
|
|
|
or %o0, %lo(xcall_flush_tlb_mm), %o0
|
|
|
|
sethi %hi(__hypervisor_xcall_flush_tlb_mm), %o1
|
|
|
|
or %o1, %lo(__hypervisor_xcall_flush_tlb_mm), %o1
|
|
|
|
call tlb_patch_one
|
2006-02-27 04:31:49 +01:00
|
|
|
mov 21, %o2
|
2006-02-04 12:08:37 +01:00
|
|
|
|
|
|
|
sethi %hi(xcall_flush_tlb_pending), %o0
|
|
|
|
or %o0, %lo(xcall_flush_tlb_pending), %o0
|
|
|
|
sethi %hi(__hypervisor_xcall_flush_tlb_pending), %o1
|
|
|
|
or %o1, %lo(__hypervisor_xcall_flush_tlb_pending), %o1
|
|
|
|
call tlb_patch_one
|
2006-02-27 04:31:49 +01:00
|
|
|
mov 21, %o2
|
2006-02-04 12:08:37 +01:00
|
|
|
|
|
|
|
sethi %hi(xcall_flush_tlb_kernel_range), %o0
|
|
|
|
or %o0, %lo(xcall_flush_tlb_kernel_range), %o0
|
|
|
|
sethi %hi(__hypervisor_xcall_flush_tlb_kernel_range), %o1
|
|
|
|
or %o1, %lo(__hypervisor_xcall_flush_tlb_kernel_range), %o1
|
|
|
|
call tlb_patch_one
|
2006-02-27 04:31:49 +01:00
|
|
|
mov 25, %o2
|
2006-02-04 12:08:37 +01:00
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
ret
|
|
|
|
restore
|