239 lines
9 KiB
C
239 lines
9 KiB
C
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/* Copyright(c) 2000, Compaq Computer Corporation
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* Fibre Channel Host Bus Adapter
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* 64-bit, 66MHz PCI
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* Originally developed and tested on:
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* (front): [chip] Tachyon TS HPFC-5166A/1.2 L2C1090 ...
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* SP# P225CXCBFIEL6T, Rev XC
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* SP# 161290-001, Rev XD
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* (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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* Written by Don Zimmerman
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*/
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#ifndef CPQFCTSCHIP_H
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#define CPQFCTSCHIP_H
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#ifndef TACHYON_CHIP_INC
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// FC-PH (Physical) specification levels for Login payloads
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// NOTE: These are NOT strictly complied with by any FC vendors
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#define FC_PH42 0x08
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#define FC_PH43 0x09
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#define FC_PH3 0x20
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#define TACHLITE_TS_RX_SIZE 1024 // max inbound frame size
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// "I" prefix is for Include
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#define IVENDID 0x00 // word
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#define IDEVID 0x02
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#define ITLCFGCMD 0x04
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#define IMEMBASE 0x18 // Tachyon
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#define ITLMEMBASE 0x1C // Tachlite
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#define IIOBASEL 0x10 // Tachyon I/O base address, lower 256 bytes
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#define IIOBASEU 0x14 // Tachyon I/O base address, upper 256 bytes
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#define ITLIOBASEL 0x14 // TachLite I/O base address, lower 256 bytes
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#define ITLIOBASEU 0x18 // TachLite I/O base address, upper 256 bytes
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#define ITLRAMBASE 0x20 // TL on-board RAM start
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#define ISROMBASE 0x24
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#define IROMBASE 0x30
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#define ICFGCMD 0x04 // PCI config - PCI config access (word)
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#define ICFGSTAT 0x06 // PCI status (R - word)
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#define IRCTR_WCTR 0x1F2 // ROM control / pre-fetch wait counter
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#define IPCIMCTR 0x1F3 // PCI master control register
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#define IINTPEND 0x1FD // Interrupt pending (I/O Upper - Tachyon & TL)
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#define IINTEN 0x1FE // Interrupt enable (I/O Upper - Tachyon & TL)
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#define IINTSTAT 0x1FF // Interrupt status (I/O Upper - Tachyon & TL)
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#define IMQ_BASE 0x80
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#define IMQ_LENGTH 0x84
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#define IMQ_CONSUMER_INDEX 0x88
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#define IMQ_PRODUCER_INDEX 0x8C // Tach copies its INDX to bits 0-7 of value
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/*
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// IOBASE UPPER
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#define SFSBQ_BASE 0x00 // single-frame sequences
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#define SFSBQ_LENGTH 0x04
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#define SFSBQ_PRODUCER_INDEX 0x08
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#define SFSBQ_CONSUMER_INDEX 0x0C // (R)
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#define SFS_BUFFER_LENGTH 0X10
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// SCSI-FCP hardware assists
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#define SEST_BASE 0x40 // SSCI Exchange State Table
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#define SEST_LENGTH 0x44
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#define SCSI_BUFFER_LENGTH 0x48
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#define SEST_LINKED_LIST 0x4C
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#define TACHYON_My_ID 0x6C
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#define TACHYON_CONFIGURATION 0x84 // (R/W) reset val 2
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#define TACHYON_CONTROL 0x88
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#define TACHYON_STATUS 0x8C // (R)
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#define TACHYON_FLUSH_SEST 0x90 // (R/W)
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#define TACHYON_EE_CREDIT_TMR 0x94 // (R)
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#define TACHYON_BB_CREDIT_TMR 0x98 // (R)
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#define TACHYON_RCV_FRAME_ERR 0x9C // (R)
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#define FRAME_MANAGER_CONFIG 0xC0 // (R/W)
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#define FRAME_MANAGER_CONTROL 0xC4
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#define FRAME_MANAGER_STATUS 0xC8 // (R)
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#define FRAME_MANAGER_ED_TOV 0xCC
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#define FRAME_MANAGER_LINK_ERR1 0xD0 // (R)
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#define FRAME_MANAGER_LINK_ERR2 0xD4 // (R)
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#define FRAME_MANAGER_TIMEOUT2 0xD8 // (W)
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#define FRAME_MANAGER_BB_CREDIT 0xDC // (R)
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#define FRAME_MANAGER_WWN_HI 0xE0 // (R/W)
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#define FRAME_MANAGER_WWN_LO 0xE4 // (R/W)
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#define FRAME_MANAGER_RCV_AL_PA 0xE8 // (R)
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#define FRAME_MANAGER_PRIMITIVE 0xEC // {K28.5} byte1 byte2 byte3
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*/
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#define TL_MEM_ERQ_BASE 0x0 //ERQ Base
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#define TL_IO_ERQ_BASE 0x0 //ERQ base
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#define TL_MEM_ERQ_LENGTH 0x4 //ERQ Length
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#define TL_IO_ERQ_LENGTH 0x4 //ERQ Length
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#define TL_MEM_ERQ_PRODUCER_INDEX 0x8 //ERQ Producer Index register
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#define TL_IO_ERQ_PRODUCER_INDEX 0x8 //ERQ Producer Index register
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#define TL_MEM_ERQ_CONSUMER_INDEX_ADR 0xC //ERQ Consumer Index address register
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#define TL_IO_ERQ_CONSUMER_INDEX_ADR 0xC //ERQ Consumer Index address register
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#define TL_MEM_ERQ_CONSUMER_INDEX 0xC //ERQ Consumer Index
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#define TL_IO_ERQ_CONSUMER_INDEX 0xC //ERQ Consumer Index
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#define TL_MEM_SFQ_BASE 0x50 //SFQ Base
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#define TL_IO_SFQ_BASE 0x50 //SFQ base
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#define TL_MEM_SFQ_LENGTH 0x54 //SFQ Length
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#define TL_IO_SFQ_LENGTH 0x54 //SFQ Length
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#define TL_MEM_SFQ_CONSUMER_INDEX 0x58 //SFQ Consumer Index
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#define TL_IO_SFQ_CONSUMER_INDEX 0x58 //SFQ Consumer Index
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#define TL_MEM_IMQ_BASE 0x80 //IMQ Base
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#define TL_IO_IMQ_BASE 0x80 //IMQ base
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#define TL_MEM_IMQ_LENGTH 0x84 //IMQ Length
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#define TL_IO_IMQ_LENGTH 0x84 //IMQ Length
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#define TL_MEM_IMQ_CONSUMER_INDEX 0x88 //IMQ Consumer Index
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#define TL_IO_IMQ_CONSUMER_INDEX 0x88 //IMQ Consumer Index
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#define TL_MEM_IMQ_PRODUCER_INDEX_ADR 0x8C //IMQ Producer Index address register
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#define TL_IO_IMQ_PRODUCER_INDEX_ADR 0x8C //IMQ Producer Index address register
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#define TL_MEM_SEST_BASE 0x140 //SFQ Base
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#define TL_IO_SEST_BASE 0x40 //SFQ base
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#define TL_MEM_SEST_LENGTH 0x144 //SFQ Length
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#define TL_IO_SEST_LENGTH 0x44 //SFQ Length
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#define TL_MEM_SEST_LINKED_LIST 0x14C
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#define TL_MEM_SEST_SG_PAGE 0x168 // Extended Scatter/Gather page size
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#define TL_MEM_TACH_My_ID 0x16C
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#define TL_IO_TACH_My_ID 0x6C //My AL_PA ID
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#define TL_MEM_TACH_CONFIG 0x184 //Tachlite Configuration register
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#define TL_IO_CONFIG 0x84 //Tachlite Configuration register
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#define TL_MEM_TACH_CONTROL 0x188 //Tachlite Control register
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#define TL_IO_CTR 0x88 //Tachlite Control register
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#define TL_MEM_TACH_STATUS 0x18C //Tachlite Status register
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#define TL_IO_STAT 0x8C //Tachlite Status register
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#define TL_MEM_FM_CONFIG 0x1C0 //Frame Manager Configuration register
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#define TL_IO_FM_CONFIG 0xC0 //Frame Manager Configuration register
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#define TL_MEM_FM_CONTROL 0x1C4 //Frame Manager Control
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#define TL_IO_FM_CTL 0xC4 //Frame Manager Control
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#define TL_MEM_FM_STATUS 0x1C8 //Frame Manager Status
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#define TL_IO_FM_STAT 0xC8 //Frame Manager Status
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#define TL_MEM_FM_LINK_STAT1 0x1D0 //Frame Manager Link Status 1
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#define TL_IO_FM_LINK_STAT1 0xD0 //Frame Manager Link Status 1
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#define TL_MEM_FM_LINK_STAT2 0x1D4 //Frame Manager Link Status 2
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#define TL_IO_FM_LINK_STAT2 0xD4 //Frame Manager Link Status 2
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#define TL_MEM_FM_TIMEOUT2 0x1D8 // (W)
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#define TL_MEM_FM_BB_CREDIT0 0x1DC
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#define TL_MEM_FM_WWN_HI 0x1E0 //Frame Manager World Wide Name High
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#define TL_IO_FM_WWN_HI 0xE0 //Frame Manager World Wide Name High
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#define TL_MEM_FM_WWN_LO 0x1E4 //Frame Manager World Wide Name LOW
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#define TL_IO_FM_WWN_LO 0xE4 //Frame Manager World Wide Name Low
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#define TL_MEM_FM_RCV_AL_PA 0x1E8 //Frame Manager AL_PA Received register
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#define TL_IO_FM_ALPA 0xE8 //Frame Manager AL_PA Received register
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#define TL_MEM_FM_ED_TOV 0x1CC
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#define TL_IO_ROMCTR 0xFA //TL PCI ROM Control Register
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#define TL_IO_PCIMCTR 0xFB //TL PCI Master Control Register
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#define TL_IO_SOFTRST 0xFC //Tachlite Configuration register
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#define TL_MEM_SOFTRST 0x1FC //Tachlite Configuration register
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// completion message types (bit 8 set means Interrupt generated)
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// CM_Type
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#define OUTBOUND_COMPLETION 0
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#define ERROR_IDLE_COMPLETION 0x01
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#define OUT_HI_PRI_COMPLETION 0x01
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#define INBOUND_MFS_COMPLETION 0x02
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#define INBOUND_000_COMPLETION 0x03
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#define INBOUND_SFS_COMPLETION 0x04 // Tachyon & TachLite
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#define ERQ_FROZEN_COMPLETION 0x06 // TachLite
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#define INBOUND_C1_TIMEOUT 0x05
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#define INBOUND_BUSIED_FRAME 0x06
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#define SFS_BUF_WARN 0x07
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#define FCP_FROZEN_COMPLETION 0x07 // TachLite
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#define MFS_BUF_WARN 0x08
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#define IMQ_BUF_WARN 0x09
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#define FRAME_MGR_INTERRUPT 0x0A
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#define READ_STATUS 0x0B
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#define INBOUND_SCSI_DATA_COMPLETION 0x0C
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#define INBOUND_FCP_XCHG_COMPLETION 0x0C // TachLite
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#define INBOUND_SCSI_DATA_COMMAND 0x0D
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#define BAD_SCSI_FRAME 0x0E
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#define INB_SCSI_STATUS_COMPLETION 0x0F
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#define BUFFER_PROCESSED_COMPLETION 0x11
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// FC-AL (Tachyon) Loop Port State Machine defs
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// (loop "Up" states)
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#define MONITORING 0x0
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#define ARBITRATING 0x1
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#define ARBITRAT_WON 0x2
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#define OPEN 0x3
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#define OPENED 0x4
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#define XMITTD_CLOSE 0x5
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#define RCVD_CLOSE 0x6
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#define TRANSFER 0x7
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// (loop "Down" states)
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#define INITIALIZING 0x8
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#define O_I_INIT 0x9
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#define O_I_PROTOCOL 0xa
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#define O_I_LIP_RCVD 0xb
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#define HOST_CONTROL 0xc
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#define LOOP_FAIL 0xd
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// (no 0xe)
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#define OLD_PORT 0xf
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#define TACHYON_CHIP_INC
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#endif
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#endif /* CPQFCTSCHIP_H */
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