2005-11-10 15:26:52 +01:00
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/*
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* linux/arch/arm/mach-omap2/clock.c
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*
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2008-03-18 10:56:39 +01:00
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2008 Nokia Corporation
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2005-11-10 15:26:52 +01:00
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*
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2008-03-18 10:56:39 +01:00
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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2005-11-10 15:26:52 +01:00
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*
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2008-03-18 10:56:39 +01:00
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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2005-11-10 15:26:52 +01:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2008-03-18 09:35:15 +01:00
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#undef DEBUG
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2005-11-10 15:26:52 +01:00
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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2006-01-07 17:15:52 +01:00
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#include <linux/clk.h>
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2008-03-18 09:35:15 +01:00
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#include <linux/io.h>
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#include <linux/cpufreq.h>
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2008-09-06 13:13:59 +02:00
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#include <linux/bitops.h>
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2005-11-10 15:26:52 +01:00
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2008-08-05 17:14:15 +02:00
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#include <mach/clock.h>
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#include <mach/sram.h>
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2006-12-13 08:02:43 +01:00
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#include <asm/div64.h>
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2009-01-19 16:27:29 +01:00
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#include <asm/clkdev.h>
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2005-11-10 15:26:52 +01:00
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2006-04-02 18:46:20 +02:00
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#include "memory.h"
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2008-03-18 09:35:15 +01:00
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#include "clock.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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2005-11-10 15:26:52 +01:00
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2008-11-04 15:02:46 +01:00
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static const struct clkops clkops_oscck;
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static const struct clkops clkops_fixed;
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#include "clock24xx.h"
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2009-01-19 16:27:29 +01:00
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struct omap_clk {
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u32 cpu;
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struct clk_lookup lk;
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};
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#define CLK(dev, con, ck, cp) \
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{ \
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.cpu = cp, \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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}, \
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}
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#define CK_243X (1 << 0)
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#define CK_242X (1 << 1)
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static struct omap_clk omap24xx_clks[] = {
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/* external root sources */
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CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
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CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
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CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
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CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
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/* internal analog sources */
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CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
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CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
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CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
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/* internal prcm root sources */
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CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
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CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
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CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
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CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
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CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
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CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
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CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
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CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
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CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
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CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
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CLK(NULL, "emul_ck", &emul_ck, CK_242X),
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/* mpu domain clocks */
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CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
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/* dsp domain clocks */
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CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
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CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
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CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
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CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
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CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
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CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
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/* GFX domain clocks */
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CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
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CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
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CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
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/* Modem domain clocks */
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CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
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CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
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/* DSS domain clocks */
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CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X),
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CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X),
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CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X),
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CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X),
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/* L3 domain clocks */
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CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
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CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
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CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
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/* L4 domain clocks */
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CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
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2009-01-28 03:12:54 +01:00
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CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
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2009-01-19 16:27:29 +01:00
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/* virtual meta-group clock */
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CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
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/* general l4 interface ck, multi-parent functional clk */
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CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
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CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
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CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
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2009-01-23 11:26:46 +01:00
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CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
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CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
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CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
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CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
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CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
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CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
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CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
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CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
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CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
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CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
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2009-01-19 21:49:37 +01:00
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CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
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CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
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CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
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CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
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CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
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CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
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2009-01-19 16:27:29 +01:00
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CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
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CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
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CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
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CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
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CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
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CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
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CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
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CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
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2009-01-19 21:44:33 +01:00
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CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
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CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
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2009-01-19 16:27:29 +01:00
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CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
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CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
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CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
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CLK(NULL, "icr_ick", &icr_ick, CK_243X),
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2009-01-24 17:27:06 +01:00
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CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
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CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
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2009-01-19 16:27:29 +01:00
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CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
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CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
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CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
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CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
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CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
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CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
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CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
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2009-01-19 21:53:30 +01:00
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CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
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CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
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2009-01-19 16:27:29 +01:00
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CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
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CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
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CLK(NULL, "eac_ick", &eac_ick, CK_242X),
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CLK(NULL, "eac_fck", &eac_fck, CK_242X),
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2009-01-22 11:12:04 +01:00
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CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
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CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
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2009-01-19 22:02:29 +01:00
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CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
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CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
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CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
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CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
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CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
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CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
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2009-01-19 16:27:29 +01:00
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CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
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CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
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CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
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CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
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CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
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CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
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CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
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CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
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2009-01-19 21:58:56 +01:00
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CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
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2009-01-19 16:27:29 +01:00
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CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
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CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
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CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
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CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
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2009-01-28 11:22:50 +01:00
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CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
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CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
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CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
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CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
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2009-01-19 16:27:29 +01:00
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CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
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CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
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CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
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CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
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CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
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};
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2008-03-18 09:35:15 +01:00
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/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
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|
#define EN_APLL_STOPPED 0
|
|
|
|
#define EN_APLL_LOCKED 3
|
2006-09-25 11:41:50 +02:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
|
|
|
|
#define APLLS_CLKIN_19_2MHZ 0
|
|
|
|
#define APLLS_CLKIN_13MHZ 2
|
|
|
|
#define APLLS_CLKIN_12MHZ 3
|
|
|
|
|
|
|
|
/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
static struct prcm_config *curr_prcm_set;
|
2006-09-25 11:41:20 +02:00
|
|
|
static struct clk *vclk;
|
|
|
|
static struct clk *sclk;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/*-------------------------------------------------------------------------
|
2008-03-18 09:35:15 +01:00
|
|
|
* Omap24xx specific clock functions
|
2005-11-10 15:26:52 +01:00
|
|
|
*-------------------------------------------------------------------------*/
|
|
|
|
|
2008-03-18 10:56:39 +01:00
|
|
|
/* This actually returns the rate of core_ck, not dpll_ck. */
|
|
|
|
static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
|
|
|
|
{
|
|
|
|
long long dpll_clk;
|
|
|
|
u8 amult;
|
|
|
|
|
|
|
|
dpll_clk = omap2_get_dpll_rate(tclk);
|
|
|
|
|
|
|
|
amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
|
|
|
amult &= OMAP24XX_CORE_CLK_SRC_MASK;
|
|
|
|
dpll_clk *= amult;
|
|
|
|
|
|
|
|
return dpll_clk;
|
|
|
|
}
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
static int omap2_enable_osc_ck(struct clk *clk)
|
|
|
|
{
|
|
|
|
u32 pcc;
|
|
|
|
|
|
|
|
pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
|
|
|
|
|
|
|
|
__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
|
|
|
|
OMAP24XX_PRCM_CLKSRC_CTRL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap2_disable_osc_ck(struct clk *clk)
|
|
|
|
{
|
|
|
|
u32 pcc;
|
|
|
|
|
|
|
|
pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
|
|
|
|
|
|
|
|
__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
|
|
|
|
OMAP24XX_PRCM_CLKSRC_CTRL);
|
|
|
|
}
|
|
|
|
|
2008-11-04 15:02:46 +01:00
|
|
|
static const struct clkops clkops_oscck = {
|
|
|
|
.enable = &omap2_enable_osc_ck,
|
|
|
|
.disable = &omap2_disable_osc_ck,
|
|
|
|
};
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
#ifdef OLD_CK
|
2005-11-10 15:26:52 +01:00
|
|
|
/* Recalculate SYST_CLK */
|
|
|
|
static void omap2_sys_clk_recalc(struct clk * clk)
|
|
|
|
{
|
|
|
|
u32 div = PRCM_CLKSRC_CTRL;
|
|
|
|
div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
|
|
|
|
div >>= clk->rate_offset;
|
|
|
|
clk->rate = (clk->parent->rate / div);
|
|
|
|
propagate_rate(clk);
|
|
|
|
}
|
2008-03-18 09:35:15 +01:00
|
|
|
#endif /* OLD_CK */
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/* Enable an APLL if off */
|
2008-03-18 09:35:15 +01:00
|
|
|
static int omap2_clk_fixed_enable(struct clk *clk)
|
2005-11-10 15:26:52 +01:00
|
|
|
{
|
2008-03-18 09:35:15 +01:00
|
|
|
u32 cval, apll_mask;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
if ((cval & apll_mask) == apll_mask)
|
|
|
|
return 0; /* apll already enabled */
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
cval &= ~apll_mask;
|
|
|
|
cval |= apll_mask;
|
|
|
|
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
if (clk == &apll96_ck)
|
2008-03-18 09:35:15 +01:00
|
|
|
cval = OMAP24XX_ST_96M_APLL;
|
2005-11-10 15:26:52 +01:00
|
|
|
else if (clk == &apll54_ck)
|
2008-03-18 09:35:15 +01:00
|
|
|
cval = OMAP24XX_ST_54M_APLL;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
|
|
|
|
clk->name);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
|
|
|
|
* fails?
|
|
|
|
*/
|
|
|
|
return 0;
|
2005-11-10 15:26:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Stop APLL */
|
|
|
|
static void omap2_clk_fixed_disable(struct clk *clk)
|
|
|
|
{
|
|
|
|
u32 cval;
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
|
|
|
cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
|
|
|
|
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
|
2005-11-10 15:26:52 +01:00
|
|
|
}
|
|
|
|
|
2008-11-04 15:02:46 +01:00
|
|
|
static const struct clkops clkops_fixed = {
|
|
|
|
.enable = &omap2_clk_fixed_enable,
|
|
|
|
.disable = &omap2_clk_fixed_disable,
|
|
|
|
};
|
|
|
|
|
2005-11-10 15:26:52 +01:00
|
|
|
/*
|
|
|
|
* Uses the current prcm set to tell if a rate is valid.
|
|
|
|
* You can go slower, but not faster within a given rate set.
|
|
|
|
*/
|
2009-01-28 03:12:50 +01:00
|
|
|
static long omap2_dpllcore_round_rate(unsigned long target_rate)
|
2005-11-10 15:26:52 +01:00
|
|
|
{
|
2008-03-18 09:35:15 +01:00
|
|
|
u32 high, low, core_clk_src;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
|
|
|
core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
|
|
|
|
|
|
|
|
if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
|
2005-11-10 15:26:52 +01:00
|
|
|
high = curr_prcm_set->dpll_speed * 2;
|
|
|
|
low = curr_prcm_set->dpll_speed;
|
|
|
|
} else { /* DPLL clockout x 2 */
|
|
|
|
high = curr_prcm_set->dpll_speed;
|
|
|
|
low = curr_prcm_set->dpll_speed / 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DOWN_VARIABLE_DPLL
|
|
|
|
if (target_rate > high)
|
|
|
|
return high;
|
|
|
|
else
|
|
|
|
return target_rate;
|
|
|
|
#else
|
|
|
|
if (target_rate > low)
|
|
|
|
return high;
|
|
|
|
else
|
|
|
|
return low;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
}
|
|
|
|
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 11:24:46 +02:00
|
|
|
static void omap2_dpllcore_recalc(struct clk *clk)
|
2008-03-18 09:35:15 +01:00
|
|
|
{
|
|
|
|
clk->rate = omap2_get_dpll_rate_24xx(clk);
|
|
|
|
}
|
2005-11-10 15:26:52 +01:00
|
|
|
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 11:24:46 +02:00
|
|
|
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
|
2005-11-10 15:26:52 +01:00
|
|
|
{
|
2008-03-18 09:35:15 +01:00
|
|
|
u32 cur_rate, low, mult, div, valid_rate, done_rate;
|
2005-11-10 15:26:52 +01:00
|
|
|
u32 bypass = 0;
|
|
|
|
struct prcm_config tmpset;
|
2008-03-18 09:35:15 +01:00
|
|
|
const struct dpll_data *dd;
|
|
|
|
unsigned long flags;
|
2005-11-10 15:26:52 +01:00
|
|
|
int ret = -EINVAL;
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
2008-03-18 09:35:15 +01:00
|
|
|
cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
|
|
|
|
mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
|
|
|
mult &= OMAP24XX_CORE_CLK_SRC_MASK;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
if ((rate == (cur_rate / 2)) && (mult == 2)) {
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
|
2005-11-10 15:26:52 +01:00
|
|
|
} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
|
2005-11-10 15:26:52 +01:00
|
|
|
} else if (rate != cur_rate) {
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 11:24:46 +02:00
|
|
|
valid_rate = omap2_dpllcore_round_rate(rate);
|
2005-11-10 15:26:52 +01:00
|
|
|
if (valid_rate != rate)
|
|
|
|
goto dpll_exit;
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
if (mult == 1)
|
2005-11-10 15:26:52 +01:00
|
|
|
low = curr_prcm_set->dpll_speed;
|
|
|
|
else
|
|
|
|
low = curr_prcm_set->dpll_speed / 2;
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
dd = clk->dpll_data;
|
|
|
|
if (!dd)
|
|
|
|
goto dpll_exit;
|
|
|
|
|
|
|
|
tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
|
|
|
|
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
|
|
|
|
dd->div1_mask);
|
2005-11-10 15:26:52 +01:00
|
|
|
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
|
2008-03-18 09:35:15 +01:00
|
|
|
tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
|
|
|
tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
|
2005-11-10 15:26:52 +01:00
|
|
|
if (rate > low) {
|
2008-03-18 09:35:15 +01:00
|
|
|
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
|
2005-11-10 15:26:52 +01:00
|
|
|
mult = ((rate / 2) / 1000000);
|
2008-03-18 09:35:15 +01:00
|
|
|
done_rate = CORE_CLK_SRC_DPLL_X2;
|
2005-11-10 15:26:52 +01:00
|
|
|
} else {
|
2008-03-18 09:35:15 +01:00
|
|
|
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
|
2005-11-10 15:26:52 +01:00
|
|
|
mult = (rate / 1000000);
|
2008-03-18 09:35:15 +01:00
|
|
|
done_rate = CORE_CLK_SRC_DPLL;
|
2005-11-10 15:26:52 +01:00
|
|
|
}
|
2008-03-18 09:35:15 +01:00
|
|
|
tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
|
|
|
|
tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/* Worst case */
|
2008-03-18 09:35:15 +01:00
|
|
|
tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
|
|
|
|
bypass = 1;
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/* Force dll lock mode */
|
|
|
|
omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
|
|
|
|
bypass);
|
|
|
|
|
|
|
|
/* Errata: ret dll entry state */
|
|
|
|
omap2_init_memory_params(omap2_dll_force_needed());
|
|
|
|
omap2_reprogram_sdrc(done_rate, 0);
|
|
|
|
}
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 11:24:46 +02:00
|
|
|
omap2_dpllcore_recalc(&dpll_ck);
|
2005-11-10 15:26:52 +01:00
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
dpll_exit:
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return(ret);
|
|
|
|
}
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
/**
|
|
|
|
* omap2_table_mpu_recalc - just return the MPU speed
|
|
|
|
* @clk: virt_prcm_set struct clk
|
|
|
|
*
|
|
|
|
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
|
|
|
|
*/
|
|
|
|
static void omap2_table_mpu_recalc(struct clk *clk)
|
2005-11-10 15:26:52 +01:00
|
|
|
{
|
|
|
|
clk->rate = curr_prcm_set->mpu_speed;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Look for a rate equal or less than the target rate given a configuration set.
|
|
|
|
*
|
|
|
|
* What's not entirely clear is "which" field represents the key field.
|
|
|
|
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
|
|
|
|
* just uses the ARM rates.
|
|
|
|
*/
|
2008-03-18 09:35:15 +01:00
|
|
|
static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
|
2005-11-10 15:26:52 +01:00
|
|
|
{
|
2008-03-18 09:35:15 +01:00
|
|
|
struct prcm_config *ptr;
|
2005-11-10 15:26:52 +01:00
|
|
|
long highest_rate;
|
|
|
|
|
|
|
|
if (clk != &virt_prcm_set)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
highest_rate = -EINVAL;
|
|
|
|
|
|
|
|
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
|
2008-03-18 09:35:15 +01:00
|
|
|
if (!(ptr->flags & cpu_mask))
|
|
|
|
continue;
|
2005-11-10 15:26:52 +01:00
|
|
|
if (ptr->xtal_speed != sys_ck.rate)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
highest_rate = ptr->mpu_speed;
|
|
|
|
|
|
|
|
/* Can check only after xtal frequency check */
|
|
|
|
if (ptr->mpu_speed <= rate)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return highest_rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Sets basic clocks based on the specified rate */
|
2008-03-18 09:35:15 +01:00
|
|
|
static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
|
2005-11-10 15:26:52 +01:00
|
|
|
{
|
2008-03-18 09:35:15 +01:00
|
|
|
u32 cur_rate, done_rate, bypass = 0, tmp;
|
2005-11-10 15:26:52 +01:00
|
|
|
struct prcm_config *prcm;
|
|
|
|
unsigned long found_speed = 0;
|
2008-03-18 09:35:15 +01:00
|
|
|
unsigned long flags;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
if (clk != &virt_prcm_set)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
|
|
|
if (!(prcm->flags & cpu_mask))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (prcm->xtal_speed != sys_ck.rate)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (prcm->mpu_speed <= rate) {
|
|
|
|
found_speed = prcm->mpu_speed;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!found_speed) {
|
|
|
|
printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
|
2008-03-18 10:56:39 +01:00
|
|
|
rate / 1000000);
|
2005-11-10 15:26:52 +01:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
curr_prcm_set = prcm;
|
2008-03-18 09:35:15 +01:00
|
|
|
cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
if (prcm->dpll_speed == cur_rate / 2) {
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
|
2005-11-10 15:26:52 +01:00
|
|
|
} else if (prcm->dpll_speed == cur_rate * 2) {
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
|
2005-11-10 15:26:52 +01:00
|
|
|
} else if (prcm->dpll_speed != cur_rate) {
|
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
|
|
if (prcm->dpll_speed == prcm->xtal_speed)
|
|
|
|
bypass = 1;
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
|
|
|
|
CORE_CLK_SRC_DPLL_X2)
|
|
|
|
done_rate = CORE_CLK_SRC_DPLL_X2;
|
2005-11-10 15:26:52 +01:00
|
|
|
else
|
2008-03-18 09:35:15 +01:00
|
|
|
done_rate = CORE_CLK_SRC_DPLL;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/* MPU divider */
|
2008-03-18 09:35:15 +01:00
|
|
|
cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/* dsp + iva1 div(2420), iva2.1(2430) */
|
2008-03-18 09:35:15 +01:00
|
|
|
cm_write_mod_reg(prcm->cm_clksel_dsp,
|
|
|
|
OMAP24XX_DSP_MOD, CM_CLKSEL);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/* Major subsystem dividers */
|
2008-03-18 09:35:15 +01:00
|
|
|
tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
|
2009-01-28 03:12:50 +01:00
|
|
|
cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
|
|
|
|
CM_CLKSEL1);
|
|
|
|
|
2005-11-10 15:26:52 +01:00
|
|
|
if (cpu_is_omap2430())
|
2008-03-18 09:35:15 +01:00
|
|
|
cm_write_mod_reg(prcm->cm_clksel_mdm,
|
|
|
|
OMAP2430_MDM_MOD, CM_CLKSEL);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
/* x2 to enter init_mem */
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
|
|
|
|
bypass);
|
|
|
|
|
|
|
|
omap2_init_memory_params(omap2_dll_force_needed());
|
|
|
|
omap2_reprogram_sdrc(done_rate, 0);
|
|
|
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 11:24:46 +02:00
|
|
|
omap2_dpllcore_recalc(&dpll_ck);
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct clk_functions omap2_clk_functions = {
|
|
|
|
.clk_enable = omap2_clk_enable,
|
|
|
|
.clk_disable = omap2_clk_disable,
|
|
|
|
.clk_round_rate = omap2_clk_round_rate,
|
|
|
|
.clk_set_rate = omap2_clk_set_rate,
|
|
|
|
.clk_set_parent = omap2_clk_set_parent,
|
2006-09-25 12:27:20 +02:00
|
|
|
.clk_disable_unused = omap2_clk_disable_unused,
|
2005-11-10 15:26:52 +01:00
|
|
|
};
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
static u32 omap2_get_apll_clkin(void)
|
2005-11-10 15:26:52 +01:00
|
|
|
{
|
2009-01-28 03:12:50 +01:00
|
|
|
u32 aplls, srate = 0;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
|
|
|
|
aplls &= OMAP24XX_APLLS_CLKIN_MASK;
|
|
|
|
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
if (aplls == APLLS_CLKIN_19_2MHZ)
|
2009-01-28 03:12:50 +01:00
|
|
|
srate = 19200000;
|
2008-03-18 09:35:15 +01:00
|
|
|
else if (aplls == APLLS_CLKIN_13MHZ)
|
2009-01-28 03:12:50 +01:00
|
|
|
srate = 13000000;
|
2008-03-18 09:35:15 +01:00
|
|
|
else if (aplls == APLLS_CLKIN_12MHZ)
|
2009-01-28 03:12:50 +01:00
|
|
|
srate = 12000000;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2009-01-28 03:12:50 +01:00
|
|
|
return srate;
|
2008-03-18 09:35:15 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static u32 omap2_get_sysclkdiv(void)
|
|
|
|
{
|
|
|
|
u32 div;
|
|
|
|
|
|
|
|
div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
|
|
|
|
div &= OMAP_SYSCLKDIV_MASK;
|
|
|
|
div >>= OMAP_SYSCLKDIV_SHIFT;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
return div;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap2_osc_clk_recalc(struct clk *clk)
|
|
|
|
{
|
|
|
|
clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap2_sys_clk_recalc(struct clk *clk)
|
|
|
|
{
|
|
|
|
clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
|
2005-11-10 15:26:52 +01:00
|
|
|
}
|
|
|
|
|
2006-09-25 11:41:20 +02:00
|
|
|
/*
|
|
|
|
* Set clocks for bypass mode for reboot to work.
|
|
|
|
*/
|
|
|
|
void omap2_clk_prepare_for_reboot(void)
|
|
|
|
{
|
|
|
|
u32 rate;
|
|
|
|
|
|
|
|
if (vclk == NULL || sclk == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
rate = clk_get_rate(sclk);
|
|
|
|
clk_set_rate(vclk, rate);
|
|
|
|
}
|
|
|
|
|
2005-11-10 15:26:52 +01:00
|
|
|
/*
|
|
|
|
* Switch the MPU rate if specified on cmdline.
|
|
|
|
* We cannot do this early until cmdline is parsed.
|
|
|
|
*/
|
|
|
|
static int __init omap2_clk_arch_init(void)
|
|
|
|
{
|
|
|
|
if (!mpurate)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (omap2_select_table_rate(&virt_prcm_set, mpurate))
|
|
|
|
printk(KERN_ERR "Could not find matching MPU rate\n");
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
recalculate_root_clocks();
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
|
|
|
|
"%ld.%01ld/%ld/%ld MHz\n",
|
|
|
|
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
|
|
|
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
arch_initcall(omap2_clk_arch_init);
|
|
|
|
|
|
|
|
int __init omap2_clk_init(void)
|
|
|
|
{
|
|
|
|
struct prcm_config *prcm;
|
2009-01-19 16:27:29 +01:00
|
|
|
struct omap_clk *c;
|
|
|
|
u32 clkrate, cpu_mask;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
if (cpu_is_omap242x())
|
|
|
|
cpu_mask = RATE_IN_242X;
|
|
|
|
else if (cpu_is_omap2430())
|
|
|
|
cpu_mask = RATE_IN_243X;
|
|
|
|
|
2005-11-10 15:26:52 +01:00
|
|
|
clk_init(&omap2_clk_functions);
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_osc_clk_recalc(&osc_ck);
|
2008-11-13 14:44:15 +01:00
|
|
|
propagate_rate(&osc_ck);
|
2008-03-18 09:35:15 +01:00
|
|
|
omap2_sys_clk_recalc(&sys_ck);
|
2008-11-13 14:44:15 +01:00
|
|
|
propagate_rate(&sys_ck);
|
2008-03-18 09:35:15 +01:00
|
|
|
|
2009-01-19 16:27:29 +01:00
|
|
|
cpu_mask = 0;
|
|
|
|
if (cpu_is_omap2420())
|
|
|
|
cpu_mask |= CK_242X;
|
|
|
|
if (cpu_is_omap2430())
|
|
|
|
cpu_mask |= CK_243X;
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2009-01-19 16:27:29 +01:00
|
|
|
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
|
|
|
|
if (c->cpu & cpu_mask) {
|
|
|
|
clkdev_add(&c->lk);
|
|
|
|
clk_register(c->lk.clk);
|
2005-11-10 15:26:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check the MPU rate set by bootloader */
|
2008-03-18 09:35:15 +01:00
|
|
|
clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
|
2005-11-10 15:26:52 +01:00
|
|
|
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
2008-03-18 09:35:15 +01:00
|
|
|
if (!(prcm->flags & cpu_mask))
|
|
|
|
continue;
|
2005-11-10 15:26:52 +01:00
|
|
|
if (prcm->xtal_speed != sys_ck.rate)
|
|
|
|
continue;
|
|
|
|
if (prcm->dpll_speed <= clkrate)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
curr_prcm_set = prcm;
|
|
|
|
|
2008-03-18 09:35:15 +01:00
|
|
|
recalculate_root_clocks();
|
2005-11-10 15:26:52 +01:00
|
|
|
|
|
|
|
printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
|
|
|
|
"%ld.%01ld/%ld/%ld MHz\n",
|
|
|
|
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
|
|
|
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only enable those clocks we will need, let the drivers
|
|
|
|
* enable other clocks as necessary
|
|
|
|
*/
|
2008-03-18 09:35:15 +01:00
|
|
|
clk_enable_init_clocks();
|
2005-11-10 15:26:52 +01:00
|
|
|
|
2006-09-25 11:41:20 +02:00
|
|
|
/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
|
|
|
|
vclk = clk_get(NULL, "virt_prcm_set");
|
|
|
|
sclk = clk_get(NULL, "sys_ck");
|
|
|
|
|
2005-11-10 15:26:52 +01:00
|
|
|
return 0;
|
|
|
|
}
|