2008-10-21 15:06:51 +02:00
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/* arch/arm/plat-s3c64xx/irq.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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2008-10-21 15:06:57 +02:00
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#include <linux/irq.h>
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2008-10-21 15:06:51 +02:00
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#include <linux/io.h>
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#include <asm/hardware/vic.h>
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#include <mach/map.h>
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2008-10-21 15:06:57 +02:00
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#include <plat/regs-timer.h>
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2008-10-21 15:06:51 +02:00
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#include <plat/cpu.h>
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2008-10-21 15:06:57 +02:00
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/* Timer interrupt handling */
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static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
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{
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generic_handle_irq(sub_irq);
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}
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static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER0);
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}
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static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER1);
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}
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static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER2);
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}
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static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER3);
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}
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static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
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{
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s3c_irq_demux_timer(irq, IRQ_TIMER4);
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}
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/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
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static void s3c_irq_timer_mask(unsigned int irq)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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reg &= 0x1f; /* mask out pending interrupts */
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reg &= ~(1 << (irq - IRQ_TIMER0));
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_unmask(unsigned int irq)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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reg &= 0x1f; /* mask out pending interrupts */
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reg |= 1 << (irq - IRQ_TIMER0);
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static void s3c_irq_timer_ack(unsigned int irq)
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{
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u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
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reg &= 0x1f;
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reg |= (1 << 5) << (irq - IRQ_TIMER0);
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__raw_writel(reg, S3C64XX_TINT_CSTAT);
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}
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static struct irq_chip s3c_irq_timer = {
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.name = "s3c-timer",
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.mask = s3c_irq_timer_mask,
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.unmask = s3c_irq_timer_unmask,
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.ack = s3c_irq_timer_ack,
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};
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2008-10-21 15:06:51 +02:00
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void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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{
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int irq;
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2008-10-21 15:06:51 +02:00
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printk(KERN_INFO "%s: initialising interrupts\n", __func__);
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/* initialise the pair of VICs */
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vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
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vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
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2008-10-21 15:06:57 +02:00
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/* add the timer sub-irqs */
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set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
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set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
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set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
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set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
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set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
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for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
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set_irq_chip(irq, &s3c_irq_timer);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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2008-10-21 15:06:51 +02:00
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}
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