2005-04-17 00:20:36 +02:00
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#ifndef _I386_PGTABLE_3LEVEL_H
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#define _I386_PGTABLE_3LEVEL_H
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/*
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* Intel Physical Address Extension (PAE) Mode - three-level page
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* tables on PPro+ CPUs.
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*
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* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
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*/
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2008-03-23 09:03:10 +01:00
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%08lx%08lx).\n", \
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__FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %p(%016Lx).\n", \
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__FILE__, __LINE__, &(e), pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p(%016Lx).\n", \
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__FILE__, __LINE__, &(e), pgd_val(e))
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2008-01-30 13:34:11 +01:00
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static inline int pud_none(pud_t pud)
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{
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return pud_val(pud) == 0;
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}
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2008-03-23 09:03:10 +01:00
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2008-01-30 13:34:11 +01:00
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static inline int pud_bad(pud_t pud)
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{
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return (pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER)) != 0;
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}
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2008-03-23 09:03:10 +01:00
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2008-01-30 13:34:11 +01:00
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static inline int pud_present(pud_t pud)
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{
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return pud_val(pud) & _PAGE_PRESENT;
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}
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2005-04-17 00:20:36 +02:00
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/* Rules for using set_pte: the pte being assigned *must* be
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* either not present or in a state where the hardware will
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* not attempt to update the pte. In places where this is
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* not possible, use pte_get_and_clear to obtain the old pte
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* value and then use set_pte to update it. -ben
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*/
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2007-05-02 19:27:13 +02:00
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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2005-04-17 00:20:36 +02:00
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{
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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2006-10-01 08:29:36 +02:00
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/*
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* Since this is only called on user PTEs, and the page fault handler
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* must handle the already racy situation of simultaneous page faults,
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* we are justified in merely clearing the PTE present bit, followed
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* by a set. The ordering here is important.
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*/
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2008-03-23 09:03:10 +01:00
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static inline void native_set_pte_present(struct mm_struct *mm,
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unsigned long addr,
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2007-05-02 19:27:13 +02:00
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pte_t *ptep, pte_t pte)
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2006-10-01 08:29:36 +02:00
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{
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ptep->pte_low = 0;
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smp_wmb();
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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2007-05-02 19:27:13 +02:00
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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2008-03-23 09:03:10 +01:00
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set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
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2007-05-02 19:27:13 +02:00
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}
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2008-03-23 09:03:10 +01:00
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2007-05-02 19:27:13 +02:00
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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2008-03-23 09:03:10 +01:00
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set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
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2007-05-02 19:27:13 +02:00
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}
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2008-03-23 09:03:10 +01:00
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2007-05-02 19:27:13 +02:00
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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2008-03-23 09:03:10 +01:00
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set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
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2007-05-02 19:27:13 +02:00
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}
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2005-04-17 00:20:36 +02:00
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[PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Proposed fix for ptep_get_and_clear_full PAE bug. Pte_clear had the same bug,
so use the same fix for both. Turns out pmd_clear had it as well, but pgds
are not affected.
The problem is rather intricate. Page table entries in PAE mode are 64-bits
wide, but the only atomic 8-byte write operation available in 32-bit mode is
cmpxchg8b, which is expensive (at least on P4), and thus avoided. But it can
happen that the processor may prefetch entries into the TLB in the middle of an
operation which clears a page table entry. So one must always clear the P-bit
in the low word of the page table entry first when clearing it.
Since the sequence *ptep = __pte(0) leaves the order of the write dependent on
the compiler, it must be coded explicitly as a clear of the low word followed
by a clear of the high word. Further, there must be a write memory barrier
here to enforce proper ordering by the compiler (and, in the future, by the
processor as well).
On > 4GB memory machines, the implementation of pte_clear for PAE was clearly
deficient, as it could leave virtual mappings of physical memory above 4GB
aliased to memory below 4GB in the TLB. The implementation of
ptep_get_and_clear_full has a similar bug, although not nearly as likely to
occur, since the mappings being cleared are in the process of being destroyed,
and should never be dereferenced again.
But, as luck would have it, it is possible to trigger bugs even without ever
dereferencing these bogus TLB mappings, even if the clear is followed fairly
soon after with a TLB flush or invalidation. The problem is that memory above
4GB may now be aliased into the first 4GB of memory, and in fact, may hit a
region of memory with non-memory semantics. These regions include AGP and PCI
space. As such, these memory regions are not cached by the processor. This
introduces the bug.
The processor can speculate memory operations, including memory writes, as long
as they are committed with the proper ordering. Speculating a memory write to
a linear address that has a bogus TLB mapping is possible. Normally, the
speculation is harmless. But for cached memory, it does leave the falsely
speculated cacheline unmodified, but in a dirty state. This cache line will be
eventually written back. If this cacheline happens to intersect a region of
memory that is not protected by the cache coherency protocol, it can corrupt
data in I/O memory, which is generally a very bad thing to do, and can cause
total system failure or just plain undefined behavior.
These bugs are extremely unlikely, but the severity is of such magnitude, and
the fix so simple that I think fixing them immediately is justified. Also,
they are nearly impossible to debug.
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-27 20:32:29 +02:00
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/*
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* For PTEs and PDEs, we must clear the P-bit first when clearing a page table
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* entry, so clear the bottom half first and enforce ordering with a compiler
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* barrier.
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*/
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2008-03-23 09:03:10 +01:00
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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[PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Proposed fix for ptep_get_and_clear_full PAE bug. Pte_clear had the same bug,
so use the same fix for both. Turns out pmd_clear had it as well, but pgds
are not affected.
The problem is rather intricate. Page table entries in PAE mode are 64-bits
wide, but the only atomic 8-byte write operation available in 32-bit mode is
cmpxchg8b, which is expensive (at least on P4), and thus avoided. But it can
happen that the processor may prefetch entries into the TLB in the middle of an
operation which clears a page table entry. So one must always clear the P-bit
in the low word of the page table entry first when clearing it.
Since the sequence *ptep = __pte(0) leaves the order of the write dependent on
the compiler, it must be coded explicitly as a clear of the low word followed
by a clear of the high word. Further, there must be a write memory barrier
here to enforce proper ordering by the compiler (and, in the future, by the
processor as well).
On > 4GB memory machines, the implementation of pte_clear for PAE was clearly
deficient, as it could leave virtual mappings of physical memory above 4GB
aliased to memory below 4GB in the TLB. The implementation of
ptep_get_and_clear_full has a similar bug, although not nearly as likely to
occur, since the mappings being cleared are in the process of being destroyed,
and should never be dereferenced again.
But, as luck would have it, it is possible to trigger bugs even without ever
dereferencing these bogus TLB mappings, even if the clear is followed fairly
soon after with a TLB flush or invalidation. The problem is that memory above
4GB may now be aliased into the first 4GB of memory, and in fact, may hit a
region of memory with non-memory semantics. These regions include AGP and PCI
space. As such, these memory regions are not cached by the processor. This
introduces the bug.
The processor can speculate memory operations, including memory writes, as long
as they are committed with the proper ordering. Speculating a memory write to
a linear address that has a bogus TLB mapping is possible. Normally, the
speculation is harmless. But for cached memory, it does leave the falsely
speculated cacheline unmodified, but in a dirty state. This cache line will be
eventually written back. If this cacheline happens to intersect a region of
memory that is not protected by the cache coherency protocol, it can corrupt
data in I/O memory, which is generally a very bad thing to do, and can cause
total system failure or just plain undefined behavior.
These bugs are extremely unlikely, but the severity is of such magnitude, and
the fix so simple that I think fixing them immediately is justified. Also,
they are nearly impossible to debug.
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-27 20:32:29 +02:00
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{
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ptep->pte_low = 0;
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smp_wmb();
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ptep->pte_high = 0;
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}
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2007-05-02 19:27:13 +02:00
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static inline void native_pmd_clear(pmd_t *pmd)
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[PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Proposed fix for ptep_get_and_clear_full PAE bug. Pte_clear had the same bug,
so use the same fix for both. Turns out pmd_clear had it as well, but pgds
are not affected.
The problem is rather intricate. Page table entries in PAE mode are 64-bits
wide, but the only atomic 8-byte write operation available in 32-bit mode is
cmpxchg8b, which is expensive (at least on P4), and thus avoided. But it can
happen that the processor may prefetch entries into the TLB in the middle of an
operation which clears a page table entry. So one must always clear the P-bit
in the low word of the page table entry first when clearing it.
Since the sequence *ptep = __pte(0) leaves the order of the write dependent on
the compiler, it must be coded explicitly as a clear of the low word followed
by a clear of the high word. Further, there must be a write memory barrier
here to enforce proper ordering by the compiler (and, in the future, by the
processor as well).
On > 4GB memory machines, the implementation of pte_clear for PAE was clearly
deficient, as it could leave virtual mappings of physical memory above 4GB
aliased to memory below 4GB in the TLB. The implementation of
ptep_get_and_clear_full has a similar bug, although not nearly as likely to
occur, since the mappings being cleared are in the process of being destroyed,
and should never be dereferenced again.
But, as luck would have it, it is possible to trigger bugs even without ever
dereferencing these bogus TLB mappings, even if the clear is followed fairly
soon after with a TLB flush or invalidation. The problem is that memory above
4GB may now be aliased into the first 4GB of memory, and in fact, may hit a
region of memory with non-memory semantics. These regions include AGP and PCI
space. As such, these memory regions are not cached by the processor. This
introduces the bug.
The processor can speculate memory operations, including memory writes, as long
as they are committed with the proper ordering. Speculating a memory write to
a linear address that has a bogus TLB mapping is possible. Normally, the
speculation is harmless. But for cached memory, it does leave the falsely
speculated cacheline unmodified, but in a dirty state. This cache line will be
eventually written back. If this cacheline happens to intersect a region of
memory that is not protected by the cache coherency protocol, it can corrupt
data in I/O memory, which is generally a very bad thing to do, and can cause
total system failure or just plain undefined behavior.
These bugs are extremely unlikely, but the severity is of such magnitude, and
the fix so simple that I think fixing them immediately is justified. Also,
they are nearly impossible to debug.
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-27 20:32:29 +02:00
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{
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u32 *tmp = (u32 *)pmd;
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*tmp = 0;
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smp_wmb();
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*(tmp + 1) = 0;
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}
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2007-05-02 19:27:13 +02:00
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2008-01-30 13:34:11 +01:00
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static inline void pud_clear(pud_t *pudp)
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{
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2008-02-04 16:48:02 +01:00
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unsigned long pgd;
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2008-01-30 13:34:11 +01:00
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set_pud(pudp, __pud(0));
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/*
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2008-02-04 16:48:02 +01:00
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* According to Intel App note "TLBs, Paging-Structure Caches,
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* and Their Invalidation", April 2007, document 317080-001,
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* section 8.1: in PAE mode we explicitly have to flush the
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* TLB via cr3 if the top-level pgd is changed...
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2008-01-30 13:34:11 +01:00
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*
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2008-02-04 16:48:02 +01:00
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* Make sure the pud entry we're updating is within the
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* current pgd to avoid unnecessary TLB flushes.
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2008-01-30 13:34:11 +01:00
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*/
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2008-02-04 16:48:02 +01:00
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pgd = read_cr3();
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2008-03-23 09:03:10 +01:00
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if (__pa(pudp) >= pgd && __pa(pudp) <
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(pgd + sizeof(pgd_t)*PTRS_PER_PGD))
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2008-02-04 16:48:02 +01:00
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write_cr3(pgd);
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2008-01-30 13:34:11 +01:00
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}
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2006-12-07 02:14:08 +01:00
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2008-03-23 09:03:10 +01:00
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#define pud_page(pud) ((struct page *) __va(pud_val(pud) & PAGE_MASK))
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2006-12-07 02:14:08 +01:00
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2008-03-23 09:03:10 +01:00
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#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
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2006-12-07 02:14:08 +01:00
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/* Find an entry in the second-level page table.. */
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2008-03-23 09:03:10 +01:00
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#define pmd_offset(pud, address) ((pmd_t *)pud_page(*(pud)) + \
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pmd_index(address))
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[PATCH] x86/PAE: Fix pte_clear for the >4GB RAM case
Proposed fix for ptep_get_and_clear_full PAE bug. Pte_clear had the same bug,
so use the same fix for both. Turns out pmd_clear had it as well, but pgds
are not affected.
The problem is rather intricate. Page table entries in PAE mode are 64-bits
wide, but the only atomic 8-byte write operation available in 32-bit mode is
cmpxchg8b, which is expensive (at least on P4), and thus avoided. But it can
happen that the processor may prefetch entries into the TLB in the middle of an
operation which clears a page table entry. So one must always clear the P-bit
in the low word of the page table entry first when clearing it.
Since the sequence *ptep = __pte(0) leaves the order of the write dependent on
the compiler, it must be coded explicitly as a clear of the low word followed
by a clear of the high word. Further, there must be a write memory barrier
here to enforce proper ordering by the compiler (and, in the future, by the
processor as well).
On > 4GB memory machines, the implementation of pte_clear for PAE was clearly
deficient, as it could leave virtual mappings of physical memory above 4GB
aliased to memory below 4GB in the TLB. The implementation of
ptep_get_and_clear_full has a similar bug, although not nearly as likely to
occur, since the mappings being cleared are in the process of being destroyed,
and should never be dereferenced again.
But, as luck would have it, it is possible to trigger bugs even without ever
dereferencing these bogus TLB mappings, even if the clear is followed fairly
soon after with a TLB flush or invalidation. The problem is that memory above
4GB may now be aliased into the first 4GB of memory, and in fact, may hit a
region of memory with non-memory semantics. These regions include AGP and PCI
space. As such, these memory regions are not cached by the processor. This
introduces the bug.
The processor can speculate memory operations, including memory writes, as long
as they are committed with the proper ordering. Speculating a memory write to
a linear address that has a bogus TLB mapping is possible. Normally, the
speculation is harmless. But for cached memory, it does leave the falsely
speculated cacheline unmodified, but in a dirty state. This cache line will be
eventually written back. If this cacheline happens to intersect a region of
memory that is not protected by the cache coherency protocol, it can corrupt
data in I/O memory, which is generally a very bad thing to do, and can cause
total system failure or just plain undefined behavior.
These bugs are extremely unlikely, but the severity is of such magnitude, and
the fix so simple that I think fixing them immediately is justified. Also,
they are nearly impossible to debug.
Signed-off-by: Zachary Amsden <zach@vmware.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-04-27 20:32:29 +02:00
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2007-05-02 19:27:19 +02:00
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#ifdef CONFIG_SMP
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2007-05-02 19:27:13 +02:00
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static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
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2005-04-17 00:20:36 +02:00
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{
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pte_t res;
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/* xchg acts as a barrier before the setting of the high bits */
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res.pte_low = xchg(&ptep->pte_low, 0);
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res.pte_high = ptep->pte_high;
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ptep->pte_high = 0;
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return res;
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}
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2007-05-02 19:27:19 +02:00
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#else
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#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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#endif
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2005-04-17 00:20:36 +02:00
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2006-09-26 08:32:30 +02:00
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#define __HAVE_ARCH_PTE_SAME
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2005-04-17 00:20:36 +02:00
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static inline int pte_same(pte_t a, pte_t b)
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{
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return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
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}
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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static inline int pte_none(pte_t pte)
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{
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return !pte.pte_low && !pte.pte_high;
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}
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static inline unsigned long pte_pfn(pte_t pte)
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{
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2008-01-30 13:32:57 +01:00
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return (pte_val(pte) & ~_PAGE_NX) >> PAGE_SHIFT;
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2005-04-17 00:20:36 +02:00
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}
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/*
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* Bits 0, 6 and 7 are taken in the low part of the pte,
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* put the 32 bits of offset into the high part.
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*/
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#define pte_to_pgoff(pte) ((pte).pte_high)
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2008-03-23 09:03:10 +01:00
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#define pgoff_to_pte(off) \
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((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
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2005-04-17 00:20:36 +02:00
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#define PTE_FILE_MAX_BITS 32
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/* Encode and de-code a swap entry */
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#define __swp_type(x) (((x).val) & 0x1f)
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#define __swp_offset(x) ((x).val >> 5)
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#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
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#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
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2008-01-30 13:32:57 +01:00
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#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } })
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2005-04-17 00:20:36 +02:00
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#endif /* _I386_PGTABLE_3LEVEL_H */
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