443 lines
12 KiB
C
443 lines
12 KiB
C
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/*
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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* Roland Dreier <rolandd@cisco.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/reg.h>
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#include <asm/io.h>
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#include <asm/ibm44x.h>
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#include "ppc440spe_pcie.h"
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static int
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pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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if (PCI_SLOT(devfn) != 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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offset += devfn << 12;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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*val = in_8(hose->cfg_data + offset);
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break;
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case 2:
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*val = in_le16(hose->cfg_data + offset);
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break;
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default:
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*val = in_le32(hose->cfg_data + offset);
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break;
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}
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if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset);
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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if (PCI_SLOT(devfn) != 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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offset += devfn << 12;
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switch (len) {
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case 1:
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out_8(hose->cfg_data + offset, val);
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break;
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case 2:
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out_le16(hose->cfg_data + offset, val);
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break;
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default:
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out_le32(hose->cfg_data + offset, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pcie_pci_ops =
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{
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.read = pcie_read_config,
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.write = pcie_write_config
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};
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enum {
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PTYPE_ENDPOINT = 0x0,
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PTYPE_LEGACY_ENDPOINT = 0x1,
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PTYPE_ROOT_PORT = 0x4,
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LNKW_X1 = 0x1,
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LNKW_X4 = 0x4,
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LNKW_X8 = 0x8
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};
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static void check_error(void)
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{
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u32 valPE0, valPE1, valPE2;
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/* SDR0_PEGPLLLCT1 reset */
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if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
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printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0);
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}
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valPE0 = SDR_READ(PESDR0_RCSSET);
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valPE1 = SDR_READ(PESDR1_RCSSET);
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valPE2 = SDR_READ(PESDR2_RCSSET);
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/* SDR0_PExRCSSET rstgu */
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if ( !(valPE0 & 0x01000000) ||
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!(valPE1 & 0x01000000) ||
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!(valPE2 & 0x01000000)) {
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printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
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}
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/* SDR0_PExRCSSET rstdl */
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if ( !(valPE0 & 0x00010000) ||
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!(valPE1 & 0x00010000) ||
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!(valPE2 & 0x00010000)) {
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printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
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}
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/* SDR0_PExRCSSET rstpyn */
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if ( (valPE0 & 0x00001000) ||
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(valPE1 & 0x00001000) ||
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(valPE2 & 0x00001000)) {
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printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
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}
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/* SDR0_PExRCSSET hldplb */
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if ( (valPE0 & 0x10000000) ||
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(valPE1 & 0x10000000) ||
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(valPE2 & 0x10000000)) {
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printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
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}
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/* SDR0_PExRCSSET rdy */
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if ( (valPE0 & 0x00100000) ||
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(valPE1 & 0x00100000) ||
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(valPE2 & 0x00100000)) {
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printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
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}
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/* SDR0_PExRCSSET shutdown */
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if ( (valPE0 & 0x00000100) ||
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(valPE1 & 0x00000100) ||
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(valPE2 & 0x00000100)) {
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printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
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}
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}
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/*
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* Initialize PCI Express core as described in User Manual section 27.12.1
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*/
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int ppc440spe_init_pcie(void)
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{
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/* Set PLL clock receiver to LVPECL */
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SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
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check_error();
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printk(KERN_INFO "PCIE initialization OK\n");
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if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
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printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
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SDR_READ(PESDR0_PLLLCT2));
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/* De-assert reset of PCIe PLL, wait for lock */
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SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
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udelay(3);
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return 0;
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}
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int ppc440spe_init_pcie_rootport(int port)
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{
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static int core_init;
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void __iomem *utl_base;
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u32 val = 0;
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int i;
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if (!core_init) {
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++core_init;
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i = ppc440spe_init_pcie();
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if (i)
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return i;
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}
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/*
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* Initialize various parts of the PCI Express core for our port:
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*
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* - Set as a root port and enable max width
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* (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
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* - Set up UTL configuration.
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* - Increase SERDES drive strength to levels suggested by AMCC.
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* - De-assert RSTPYN, RSTDL and RSTGU.
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*/
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switch (port) {
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case 0:
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SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
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SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
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SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
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SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
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SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
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SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
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SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
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SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
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SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
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SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
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SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
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SDR_WRITE(PESDR0_RCSSET,
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(SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
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break;
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case 1:
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SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
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SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
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SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
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SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
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SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
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SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
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SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
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SDR_WRITE(PESDR1_RCSSET,
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(SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
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break;
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case 2:
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SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
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SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
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SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
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SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
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SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
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SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
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SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
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SDR_WRITE(PESDR2_RCSSET,
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(SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
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break;
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}
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mdelay(1000);
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switch (port) {
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case 0: val = SDR_READ(PESDR0_RCSSTS); break;
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case 1: val = SDR_READ(PESDR1_RCSSTS); break;
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case 2: val = SDR_READ(PESDR2_RCSSTS); break;
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}
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if (!(val & (1 << 20)))
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printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
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else
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printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);
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switch (port) {
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case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
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case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
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case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
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}
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/*
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* Map UTL registers at 0xc_1000_0n00
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*/
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switch (port) {
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case 0:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
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break;
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case 1:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
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break;
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case 2:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
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}
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utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100);
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/*
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* Set buffer allocations and then assert VRB and TXE.
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*/
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out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
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out_be32(utl_base + PEUTL_INTR, 0x02000000);
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out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
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out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
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out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
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out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
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out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
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out_be32(utl_base + PEUTL_PCTL, 0x80800066);
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iounmap(utl_base);
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/*
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* We map PCI Express configuration access into the 512MB regions
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* PCIE0: 0xc_4000_0000
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* PCIE1: 0xc_8000_0000
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* PCIE2: 0xc_c000_0000
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*/
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switch (port) {
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case 0:
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
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break;
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case 1:
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
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break;
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case 2:
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mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
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mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
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mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
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break;
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}
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/*
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* Check for VC0 active and assert RDY.
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*/
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switch (port) {
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case 0:
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if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
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printk(KERN_WARNING "PCIE0: VC0 not active\n");
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SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
|
||
|
|
printk(KERN_WARNING "PCIE0: VC0 not active\n");
|
||
|
|
SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
|
||
|
|
printk(KERN_WARNING "PCIE0: VC0 not active\n");
|
||
|
|
SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if 0
|
||
|
|
/* Dump all config regs */
|
||
|
|
for (i = 0x300; i <= 0x320; ++i)
|
||
|
|
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
|
||
|
|
for (i = 0x340; i <= 0x353; ++i)
|
||
|
|
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
|
||
|
|
for (i = 0x370; i <= 0x383; ++i)
|
||
|
|
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
|
||
|
|
for (i = 0x3a0; i <= 0x3a2; ++i)
|
||
|
|
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
|
||
|
|
for (i = 0x3c0; i <= 0x3c3; ++i)
|
||
|
|
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
mdelay(100);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
|
||
|
|
{
|
||
|
|
void __iomem *mbase;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Map 16MB, which is enough for 4 bits of bus #
|
||
|
|
*/
|
||
|
|
hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000,
|
||
|
|
1 << 24);
|
||
|
|
hose->ops = &pcie_pci_ops;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set bus numbers on our root port
|
||
|
|
*/
|
||
|
|
mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096);
|
||
|
|
out_8(mbase + PCI_PRIMARY_BUS, 0);
|
||
|
|
out_8(mbase + PCI_SECONDARY_BUS, 0);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set up outbound translation to hose->mem_space from PLB
|
||
|
|
* addresses at an offset of 0xd_0000_0000. We set the low
|
||
|
|
* bits of the mask to 11 to turn off splitting into 8
|
||
|
|
* subregions and to enable the outbound translation.
|
||
|
|
*/
|
||
|
|
out_le32(mbase + PECFG_POM0LAH, 0);
|
||
|
|
out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start);
|
||
|
|
|
||
|
|
switch (port) {
|
||
|
|
case 0:
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
|
||
|
|
~(hose->mem_space.end - hose->mem_space.start) | 3);
|
||
|
|
break;
|
||
|
|
case 1:
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
|
||
|
|
~(hose->mem_space.end - hose->mem_space.start) | 3);
|
||
|
|
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
|
||
|
|
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
|
||
|
|
~(hose->mem_space.end - hose->mem_space.start) | 3);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set up 16GB inbound memory window at 0 */
|
||
|
|
out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
|
||
|
|
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
|
||
|
|
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
|
||
|
|
out_le32(mbase + PECFG_BAR0LMPA, 0);
|
||
|
|
out_le32(mbase + PECFG_PIM0LAL, 0);
|
||
|
|
out_le32(mbase + PECFG_PIM0LAH, 0);
|
||
|
|
out_le32(mbase + PECFG_PIMEN, 0x1);
|
||
|
|
|
||
|
|
/* Enable I/O, Mem, and Busmaster cycles */
|
||
|
|
out_le16(mbase + PCI_COMMAND,
|
||
|
|
in_le16(mbase + PCI_COMMAND) |
|
||
|
|
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
||
|
|
|
||
|
|
iounmap(mbase);
|
||
|
|
}
|