486 lines
13 KiB
C
486 lines
13 KiB
C
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/*
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* linux/drivers/ide/pci/aec62xx.c Version 0.11 March 27, 2002
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*
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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*
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*/
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#include <linux/module.h>
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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struct chipset_bus_clock_list_entry {
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u8 xfer_speed;
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u8 chipset_settings;
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u8 ultra_settings;
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};
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static struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
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{ XFER_UDMA_6, 0x31, 0x07 },
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{ XFER_UDMA_5, 0x31, 0x06 },
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{ XFER_UDMA_4, 0x31, 0x05 },
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{ XFER_UDMA_3, 0x31, 0x04 },
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{ XFER_UDMA_2, 0x31, 0x03 },
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{ XFER_UDMA_1, 0x31, 0x02 },
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{ XFER_UDMA_0, 0x31, 0x01 },
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{ XFER_MW_DMA_2, 0x31, 0x00 },
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{ XFER_MW_DMA_1, 0x31, 0x00 },
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{ XFER_MW_DMA_0, 0x0a, 0x00 },
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{ XFER_PIO_4, 0x31, 0x00 },
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{ XFER_PIO_3, 0x33, 0x00 },
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{ XFER_PIO_2, 0x08, 0x00 },
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{ XFER_PIO_1, 0x0a, 0x00 },
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{ XFER_PIO_0, 0x00, 0x00 },
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{ 0, 0x00, 0x00 }
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};
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static struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
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{ XFER_UDMA_6, 0x41, 0x06 },
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{ XFER_UDMA_5, 0x41, 0x05 },
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{ XFER_UDMA_4, 0x41, 0x04 },
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{ XFER_UDMA_3, 0x41, 0x03 },
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{ XFER_UDMA_2, 0x41, 0x02 },
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{ XFER_UDMA_1, 0x41, 0x01 },
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{ XFER_UDMA_0, 0x41, 0x01 },
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{ XFER_MW_DMA_2, 0x41, 0x00 },
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{ XFER_MW_DMA_1, 0x42, 0x00 },
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{ XFER_MW_DMA_0, 0x7a, 0x00 },
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{ XFER_PIO_4, 0x41, 0x00 },
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{ XFER_PIO_3, 0x43, 0x00 },
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{ XFER_PIO_2, 0x78, 0x00 },
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{ XFER_PIO_1, 0x7a, 0x00 },
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{ XFER_PIO_0, 0x70, 0x00 },
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{ 0, 0x00, 0x00 }
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};
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#define BUSCLOCK(D) \
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((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
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#if 0
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if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
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(void) pci_read_config_byte(dev, 0x54, &art);
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p += sprintf(p, "DMA Mode: %s(%s)",
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(c0&0x20)?((art&0x03)?"UDMA":" DMA"):" PIO",
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(art&0x02)?"2":(art&0x01)?"1":"0");
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p += sprintf(p, " %s(%s)",
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(c0&0x40)?((art&0x0c)?"UDMA":" DMA"):" PIO",
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(art&0x08)?"2":(art&0x04)?"1":"0");
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p += sprintf(p, " %s(%s)",
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(c1&0x20)?((art&0x30)?"UDMA":" DMA"):" PIO",
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(art&0x20)?"2":(art&0x10)?"1":"0");
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p += sprintf(p, " %s(%s)\n",
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(c1&0x40)?((art&0xc0)?"UDMA":" DMA"):" PIO",
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(art&0x80)?"2":(art&0x40)?"1":"0");
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} else {
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#endif
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/*
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* TO DO: active tuning and correction of cards without a bios.
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*/
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static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
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{
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for ( ; chipset_table->xfer_speed ; chipset_table++)
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if (chipset_table->xfer_speed == speed) {
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return chipset_table->chipset_settings;
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}
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return chipset_table->chipset_settings;
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}
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static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
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{
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for ( ; chipset_table->xfer_speed ; chipset_table++)
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if (chipset_table->xfer_speed == speed) {
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return chipset_table->ultra_settings;
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}
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return chipset_table->ultra_settings;
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}
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static u8 aec62xx_ratemask (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u8 mode;
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switch(hwif->pci_dev->device) {
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case PCI_DEVICE_ID_ARTOP_ATP865:
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case PCI_DEVICE_ID_ARTOP_ATP865R:
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#if 0
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mode = (hwif->INB(hwif->dma_master) & 0x10) ? 4 : 3;
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#else
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mode = (hwif->INB(((hwif->channel) ?
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hwif->mate->dma_status :
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hwif->dma_status)) & 0x10) ? 4 : 3;
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#endif
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break;
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case PCI_DEVICE_ID_ARTOP_ATP860:
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case PCI_DEVICE_ID_ARTOP_ATP860R:
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mode = 2;
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break;
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case PCI_DEVICE_ID_ARTOP_ATP850UF:
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default:
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return 1;
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}
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if (!eighty_ninty_three(drive))
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mode = min(mode, (u8)1);
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return mode;
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}
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static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u16 d_conf = 0;
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u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
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u8 ultra = 0, ultra_conf = 0;
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u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
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unsigned long flags;
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local_irq_save(flags);
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/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
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pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
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tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
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d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
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pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
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tmp1 = 0x00;
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tmp2 = 0x00;
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pci_read_config_byte(dev, 0x54, &ultra);
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tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
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ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
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tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
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pci_write_config_byte(dev, 0x54, tmp2);
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local_irq_restore(flags);
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return(ide_config_drive_speed(drive, speed));
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}
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static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
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u8 unit = (drive->select.b.unit & 0x01);
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u8 tmp1 = 0, tmp2 = 0;
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u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
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unsigned long flags;
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local_irq_save(flags);
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/* high 4-bits: Active, low 4-bits: Recovery */
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pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
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drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
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pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
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pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
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tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
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ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
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tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
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pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
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local_irq_restore(flags);
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return(ide_config_drive_speed(drive, speed));
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}
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static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
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{
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switch (HWIF(drive)->pci_dev->device) {
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case PCI_DEVICE_ID_ARTOP_ATP865:
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case PCI_DEVICE_ID_ARTOP_ATP865R:
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case PCI_DEVICE_ID_ARTOP_ATP860:
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case PCI_DEVICE_ID_ARTOP_ATP860R:
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return ((int) aec6260_tune_chipset(drive, speed));
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case PCI_DEVICE_ID_ARTOP_ATP850UF:
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return ((int) aec6210_tune_chipset(drive, speed));
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default:
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return -1;
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}
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}
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static int config_chipset_for_dma (ide_drive_t *drive)
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{
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u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));
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if (!(speed))
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return 0;
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(void) aec62xx_tune_chipset(drive, speed);
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return ide_dma_enable(drive);
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}
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static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
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{
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u8 speed = 0;
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u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
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switch(pio) {
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case 5: speed = new_pio; break;
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case 4: speed = XFER_PIO_4; break;
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case 3: speed = XFER_PIO_3; break;
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case 2: speed = XFER_PIO_2; break;
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case 1: speed = XFER_PIO_1; break;
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default: speed = XFER_PIO_0; break;
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}
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(void) aec62xx_tune_chipset(drive, speed);
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}
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static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct hd_driveid *id = drive->id;
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if ((id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive)) {
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if (config_chipset_for_dma(drive))
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return hwif->ide_dma_on(drive);
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}
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goto fast_ata_pio;
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} else if ((id->capability & 8) || (id->field_valid & 2)) {
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fast_ata_pio:
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aec62xx_tune_drive(drive, 5);
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return hwif->ide_dma_off_quietly(drive);
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}
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/* IORDY not supported */
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return 0;
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}
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static int aec62xx_irq_timeout (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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switch(dev->device) {
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case PCI_DEVICE_ID_ARTOP_ATP860:
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case PCI_DEVICE_ID_ARTOP_ATP860R:
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case PCI_DEVICE_ID_ARTOP_ATP865:
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case PCI_DEVICE_ID_ARTOP_ATP865R:
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printk(" AEC62XX time out ");
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#if 0
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{
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int i = 0;
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u8 reg49h = 0;
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pci_read_config_byte(HWIF(drive)->pci_dev, 0x49, ®49h);
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for (i=0;i<256;i++)
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pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h|0x10);
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pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h & ~0x10);
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}
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return 0;
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#endif
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default:
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break;
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}
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#if 0
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 tmp1 = 0, tmp2 = 0, mode6 = 0;
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pci_read_config_byte(dev, 0x44, &tmp1);
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pci_read_config_byte(dev, 0x45, &tmp2);
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printk(" AEC6280 r44=%x r45=%x ",tmp1,tmp2);
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mode6 = HWIF(drive)->INB(((hwif->channel) ?
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hwif->mate->dma_status :
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hwif->dma_status));
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printk(" AEC6280 133=%x ", (mode6 & 0x10));
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}
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#endif
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return 0;
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}
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static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
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{
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int bus_speed = system_bus_clock();
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if (dev->resource[PCI_ROM_RESOURCE].start) {
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
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printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
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}
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if (bus_speed <= 33)
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pci_set_drvdata(dev, (void *) aec6xxx_33_base);
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else
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pci_set_drvdata(dev, (void *) aec6xxx_34_base);
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return dev->irq;
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}
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static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
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{
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hwif->autodma = 0;
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hwif->tuneproc = &aec62xx_tune_drive;
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hwif->speedproc = &aec62xx_tune_chipset;
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if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
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hwif->serialized = hwif->channel;
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hwif->no_dsc = 1;
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}
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if (hwif->mate)
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hwif->mate->serialized = hwif->serialized;
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if (!hwif->dma_base) {
|
||
|
|
hwif->drives[0].autotune = 1;
|
||
|
|
hwif->drives[1].autotune = 1;
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
hwif->ultra_mask = 0x7f;
|
||
|
|
hwif->mwdma_mask = 0x07;
|
||
|
|
hwif->swdma_mask = 0x07;
|
||
|
|
|
||
|
|
hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
|
||
|
|
hwif->ide_dma_lostirq = &aec62xx_irq_timeout;
|
||
|
|
hwif->ide_dma_timeout = &aec62xx_irq_timeout;
|
||
|
|
if (!noautodma)
|
||
|
|
hwif->autodma = 1;
|
||
|
|
hwif->drives[0].autodma = hwif->autodma;
|
||
|
|
hwif->drives[1].autodma = hwif->autodma;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
|
||
|
|
{
|
||
|
|
struct pci_dev *dev = hwif->pci_dev;
|
||
|
|
|
||
|
|
if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
|
||
|
|
u8 reg54h = 0;
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&ide_lock, flags);
|
||
|
|
pci_read_config_byte(dev, 0x54, ®54h);
|
||
|
|
pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
|
||
|
|
spin_unlock_irqrestore(&ide_lock, flags);
|
||
|
|
} else {
|
||
|
|
u8 ata66 = 0;
|
||
|
|
pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
|
||
|
|
if (!(hwif->udma_four))
|
||
|
|
hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
|
||
|
|
}
|
||
|
|
|
||
|
|
ide_setup_dma(hwif, dmabase, 8);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
|
||
|
|
{
|
||
|
|
return ide_setup_pci_device(dev, d);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
|
||
|
|
{
|
||
|
|
unsigned long bar4reg = pci_resource_start(dev, 4);
|
||
|
|
|
||
|
|
if (inb(bar4reg+2) & 0x10) {
|
||
|
|
strcpy(d->name, "AEC6880");
|
||
|
|
if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
|
||
|
|
strcpy(d->name, "AEC6880R");
|
||
|
|
} else {
|
||
|
|
strcpy(d->name, "AEC6280");
|
||
|
|
if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
|
||
|
|
strcpy(d->name, "AEC6280R");
|
||
|
|
}
|
||
|
|
|
||
|
|
return ide_setup_pci_device(dev, d);
|
||
|
|
}
|
||
|
|
|
||
|
|
static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
|
||
|
|
{ /* 0 */
|
||
|
|
.name = "AEC6210",
|
||
|
|
.init_setup = init_setup_aec62xx,
|
||
|
|
.init_chipset = init_chipset_aec62xx,
|
||
|
|
.init_hwif = init_hwif_aec62xx,
|
||
|
|
.init_dma = init_dma_aec62xx,
|
||
|
|
.channels = 2,
|
||
|
|
.autodma = AUTODMA,
|
||
|
|
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
|
||
|
|
.bootable = OFF_BOARD,
|
||
|
|
},{ /* 1 */
|
||
|
|
.name = "AEC6260",
|
||
|
|
.init_setup = init_setup_aec62xx,
|
||
|
|
.init_chipset = init_chipset_aec62xx,
|
||
|
|
.init_hwif = init_hwif_aec62xx,
|
||
|
|
.init_dma = init_dma_aec62xx,
|
||
|
|
.channels = 2,
|
||
|
|
.autodma = NOAUTODMA,
|
||
|
|
.bootable = OFF_BOARD,
|
||
|
|
},{ /* 2 */
|
||
|
|
.name = "AEC6260R",
|
||
|
|
.init_setup = init_setup_aec62xx,
|
||
|
|
.init_chipset = init_chipset_aec62xx,
|
||
|
|
.init_hwif = init_hwif_aec62xx,
|
||
|
|
.init_dma = init_dma_aec62xx,
|
||
|
|
.channels = 2,
|
||
|
|
.autodma = AUTODMA,
|
||
|
|
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
|
||
|
|
.bootable = NEVER_BOARD,
|
||
|
|
},{ /* 3 */
|
||
|
|
.name = "AEC6X80",
|
||
|
|
.init_setup = init_setup_aec6x80,
|
||
|
|
.init_chipset = init_chipset_aec62xx,
|
||
|
|
.init_hwif = init_hwif_aec62xx,
|
||
|
|
.init_dma = init_dma_aec62xx,
|
||
|
|
.channels = 2,
|
||
|
|
.autodma = AUTODMA,
|
||
|
|
.bootable = OFF_BOARD,
|
||
|
|
},{ /* 4 */
|
||
|
|
.name = "AEC6X80R",
|
||
|
|
.init_setup = init_setup_aec6x80,
|
||
|
|
.init_chipset = init_chipset_aec62xx,
|
||
|
|
.init_hwif = init_hwif_aec62xx,
|
||
|
|
.init_dma = init_dma_aec62xx,
|
||
|
|
.channels = 2,
|
||
|
|
.autodma = AUTODMA,
|
||
|
|
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
|
||
|
|
.bootable = OFF_BOARD,
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* aec62xx_init_one - called when a AEC is found
|
||
|
|
* @dev: the aec62xx device
|
||
|
|
* @id: the matching pci id
|
||
|
|
*
|
||
|
|
* Called when the PCI registration layer (or the IDE initialization)
|
||
|
|
* finds a device matching our IDE device tables.
|
||
|
|
*/
|
||
|
|
|
||
|
|
static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||
|
|
{
|
||
|
|
ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
|
||
|
|
|
||
|
|
return d->init_setup(dev, d);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct pci_device_id aec62xx_pci_tbl[] = {
|
||
|
|
{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
|
||
|
|
{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
|
||
|
|
{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
|
||
|
|
{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
|
||
|
|
{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
|
||
|
|
{ 0, },
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
|
||
|
|
|
||
|
|
static struct pci_driver driver = {
|
||
|
|
.name = "AEC62xx_IDE",
|
||
|
|
.id_table = aec62xx_pci_tbl,
|
||
|
|
.probe = aec62xx_init_one,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int aec62xx_ide_init(void)
|
||
|
|
{
|
||
|
|
return ide_pci_register_driver(&driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(aec62xx_ide_init);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Andre Hedrick");
|
||
|
|
MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
|
||
|
|
MODULE_LICENSE("GPL");
|