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ARM: Provide common header for hard_smp_processor_id()

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Provide a common header to read the SMP CPU number from the MPIDR.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2010-09-04 16:14:20 +01:00
parent 971acb9b42
commit 067173526c
7 changed files with 18 additions and 53 deletions
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12
arch/arm/include/asm/smp_mpidr.h Normal file
View file

@ -0,0 +1,12 @@
#ifndef ASMARM_SMP_MIDR_H
#define ASMARM_SMP_MIDR_H
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5\n" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
#endif

10
arch/arm/mach-realview/include/mach/smp.h
View file

@ -1,16 +1,8 @@
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <asm/hardware/gic.h>
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
#include <asm/smp_mpidr.h>
/*
* We use IRQ1 as the IPI

9
arch/arm/mach-s5pv310/include/mach/smp.h
View file

@ -7,17 +7,10 @@
#define ASM_ARCH_SMP_H __FILE__
#include <asm/hardware/gic.h>
#include <asm/smp_mpidr.h>
extern void __iomem *gic_cpu_base_addr;
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x03; \
})
/*
* We use IRQ1 as the IPI
*/

10
arch/arm/mach-tegra/include/mach/smp.h
View file

@ -1,16 +1,8 @@
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <asm/hardware/gic.h>
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
#include <asm/smp_mpidr.h>
/*
* We use IRQ1 as the IPI

9
arch/arm/mach-ux500/include/mach/smp.h
View file

@ -10,18 +10,11 @@
#define ASMARM_ARCH_SMP_H
#include <asm/hardware/gic.h>
#include <asm/smp_mpidr.h>
/* This is required to wakeup the secondary core */
extern void u8500_secondary_startup(void);
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
/*
* We use IRQ1 as the IPI
*/

9
arch/arm/mach-vexpress/include/mach/smp.h
View file

@ -2,14 +2,7 @@
#define __MACH_SMP_H
#include <asm/hardware/gic.h>
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
#include <asm/smp_mpidr.h>
/*
* We use IRQ1 as the IPI

12
arch/arm/plat-omap/include/plat/smp.h
View file

@ -18,6 +18,7 @@
#define OMAP_ARCH_SMP_H
#include <asm/hardware/gic.h>
#include <asm/smp_mpidr.h>
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
gic_raise_softirq(mask, 1);
}
/*
* Read MPIDR: Multiprocessor affinity register
*/
#define hard_smp_processor_id() \
({ \
unsigned int cpunum; \
__asm__("mrc p15, 0, %0, c0, c0, 5" \
: "=r" (cpunum)); \
cpunum &= 0x0F; \
})
#endif