dmaengine: rcar-dmac: enable descriptor mode on 40bit
SYS-DMAC can use 40bit address transfer, and it supports Descriptor Mode too. Current SYS-DMAC driver disables Descriptor Mode if it was 40bit address today. But it can use Descriptor Mode with 40bit if transfer Source/Destination address are located in same 4GiB region in the 40 bit address space. This patch enables it if all condition was clear Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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1 changed files with 32 additions and 20 deletions
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@ -344,13 +344,19 @@ static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
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rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
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rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
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if (desc->hwdescs.use) {
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if (desc->hwdescs.use) {
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struct rcar_dmac_xfer_chunk *chunk;
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struct rcar_dmac_xfer_chunk *chunk =
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list_first_entry(&desc->chunks,
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struct rcar_dmac_xfer_chunk, node);
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dev_dbg(chan->chan.device->dev,
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dev_dbg(chan->chan.device->dev,
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"chan%u: queue desc %p: %u@%pad\n",
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"chan%u: queue desc %p: %u@%pad\n",
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chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
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chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
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chunk->src_addr >> 32);
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rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
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chunk->dst_addr >> 32);
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rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
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rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
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desc->hwdescs.dma >> 32);
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desc->hwdescs.dma >> 32);
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#endif
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#endif
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@ -368,8 +374,6 @@ static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
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* should. Initialize it manually with the destination address
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* should. Initialize it manually with the destination address
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* of the first chunk.
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* of the first chunk.
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*/
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*/
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chunk = list_first_entry(&desc->chunks,
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struct rcar_dmac_xfer_chunk, node);
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rcar_dmac_chan_write(chan, RCAR_DMADAR,
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rcar_dmac_chan_write(chan, RCAR_DMADAR,
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chunk->dst_addr & 0xffffffff);
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chunk->dst_addr & 0xffffffff);
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@ -855,8 +859,12 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
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unsigned int nchunks = 0;
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unsigned int nchunks = 0;
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unsigned int max_chunk_size;
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unsigned int max_chunk_size;
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unsigned int full_size = 0;
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unsigned int full_size = 0;
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bool highmem = false;
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bool cross_boundary = false;
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unsigned int i;
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unsigned int i;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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u32 high_dev_addr;
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u32 high_mem_addr;
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#endif
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desc = rcar_dmac_desc_get(chan);
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desc = rcar_dmac_desc_get(chan);
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if (!desc)
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if (!desc)
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@ -882,6 +890,16 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
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full_size += len;
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full_size += len;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (i == 0) {
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high_dev_addr = dev_addr >> 32;
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high_mem_addr = mem_addr >> 32;
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}
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if ((dev_addr >> 32 != high_dev_addr) ||
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(mem_addr >> 32 != high_mem_addr))
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cross_boundary = true;
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#endif
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while (len) {
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while (len) {
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unsigned int size = min(len, max_chunk_size);
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unsigned int size = min(len, max_chunk_size);
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@ -890,18 +908,14 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
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* Prevent individual transfers from crossing 4GB
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* Prevent individual transfers from crossing 4GB
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* boundaries.
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* boundaries.
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*/
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*/
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if (dev_addr >> 32 != (dev_addr + size - 1) >> 32)
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if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) {
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size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
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size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
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if (mem_addr >> 32 != (mem_addr + size - 1) >> 32)
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cross_boundary = true;
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}
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if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) {
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size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
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size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
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cross_boundary = true;
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/*
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}
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* Check if either of the source or destination address
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* can't be expressed in 32 bits. If so we can't use
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* hardware descriptor lists.
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*/
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if (dev_addr >> 32 || mem_addr >> 32)
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highmem = true;
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#endif
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#endif
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chunk = rcar_dmac_xfer_chunk_get(chan);
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chunk = rcar_dmac_xfer_chunk_get(chan);
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@ -943,13 +957,11 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
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* Use hardware descriptor lists if possible when more than one chunk
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* Use hardware descriptor lists if possible when more than one chunk
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* needs to be transferred (otherwise they don't make much sense).
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* needs to be transferred (otherwise they don't make much sense).
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*
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*
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* The highmem check currently covers the whole transfer. As an
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* Source/Destination address should be located in same 4GiB region
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* optimization we could use descriptor lists for consecutive lowmem
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* in the 40bit address space when it uses Hardware descriptor,
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* chunks and direct manual mode for highmem chunks. Whether the
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* and cross_boundary is checking it.
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* performance improvement would be significant enough compared to the
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* additional complexity remains to be investigated.
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*/
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*/
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desc->hwdescs.use = !highmem && nchunks > 1;
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desc->hwdescs.use = !cross_boundary && nchunks > 1;
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if (desc->hwdescs.use) {
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if (desc->hwdescs.use) {
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if (rcar_dmac_fill_hwdesc(chan, desc) < 0)
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if (rcar_dmac_fill_hwdesc(chan, desc) < 0)
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desc->hwdescs.use = false;
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desc->hwdescs.use = false;
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