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Allwinner DT additions for 3.17

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Among the few patches that we have so far, there's a few noticeable changes:
   - Introduction of the Allwinner A23 SoC
   - Support for the GMAC on the A31. This is only available so far on the
     boards which bootloader enable the PHY regulator.
   - Addition of the infrared receiver
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Merge tag 'sunxi-dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt

Merge "Allwinner DT additions for 3.17" from Maxime Ripard:

Among the few patches that we have so far, there's a few noticeable changes:
 - Introduction of the Allwinner A23 SoC
 - Support for the GMAC on the A31. This is only available so far on the
   boards which bootloader enable the PHY regulator.
 - Addition of the infrared receiver

* tag 'sunxi-dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (22 commits)
  ARM: dts: sun6i: Add Merrii A31 Hummingbird support
  ARM: dts: sun6i: Add ethernet alias for GMAC
  ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node
  ARM: dts: sun6i: Add GMAC clock node to the A31 dtsi
  ARM: dts: sun6i: Add pin muxing options for GMAC
  ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI
  ARM: sun8i: Add reset controller nodes to the DTSI
  ARM: sun8i: Add basic clock nodes to the DTSI
  ARM: dts: sun4i: Add ir node to various boards
  ARM: dts: sun4i: Add ir controller nodes and pinmux
  ARM: dts: sun4i: Add new ba10-tvbox board
  ARM: dts: sun7i: Add board support for LinkSprite pcDuino V3
  ARM: dts: sun7i: Add ir receiver support to a20-i12-tvbox
  ARM: dts: sun7i: Rename sun7i-a20-ir to sun4i-a10-ir
  ARM: dts: sun7i: Add AXP209 support to various boards
  ARM: dts: sun4i: Add AXP209 support to various boards
  ARM: dts: sunxi: Add #interrupt-cells to pinctrl nodes
  ARM: sun8i: dt: Add Ippo-q8h v5 support
  ARM: sunxi: Add Allwinner A23 dtsi
  ARM: sunxi: Add IR controllers on A20 to dtsi
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-07-19 12:19:28 -07:00
commit 15bebad68e
22 changed files with 1121 additions and 13 deletions
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7
arch/arm/boot/dts/Makefile
View file

@ -381,6 +381,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
stih416-b2020e.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
sun4i-a10-cubieboard.dtb \
sun4i-a10-mini-xplus.dtb \
sun4i-a10-hackberry.dtb \
@ -395,12 +396,16 @@ dtb-$(CONFIG_MACH_SUN5I) += \
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
sun6i-a31-hummingbird.dtb \
sun6i-a31-m9.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-olinuxino-micro.dtb
sun7i-a20-olinuxino-micro.dtb \
sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
tegra20-medcom-wide.dtb \

15
arch/arm/boot/dts/sun4i-a10-a1000.dts
View file

@ -88,6 +88,12 @@
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@ -98,6 +104,15 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

110
arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts Normal file
View file

@ -0,0 +1,110 @@
/*
* Copyright 2014 Hans de Goede <hdegoede@redhat.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun4i-a10.dtsi"
/include/ "sunxi-common-regulators.dtsi"
/ {
model = "BA10 tvbox";
compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10";
soc@01c00000 {
emac: ethernet@01c0b000 {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins_a>;
phy = <&phy1>;
status = "okay";
};
mdio@01c0b080 {
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
mmc0: mmc@01c0f000 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 0>; /* PH1 */
cd-inverted;
status = "okay";
};
usbphy: phy@01c13400 {
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};
ehci0: usb@01c14000 {
status = "okay";
};
ohci0: usb@01c14400 {
status = "okay";
};
ehci1: usb@01c1c000 {
status = "okay";
};
ohci1: usb@01c1c400 {
status = "okay";
};
pinctrl@01c20800 {
usb2_vbus_pin_a: usb2_vbus_pin@0 {
allwinner,pins = "PH12";
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
reg_usb1_vbus: usb1-vbus {
status = "okay";
};
reg_usb2_vbus: usb2-vbus {
gpio = <&pio 7 12 0>;
status = "okay";
};
};

15
arch/arm/boot/dts/sun4i-a10-cubieboard.dts
View file

@ -80,6 +80,12 @@
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@ -90,6 +96,15 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
i2c1: i2c@01c2b000 {

21
arch/arm/boot/dts/sun4i-a10-hackberry.dts
View file

@ -87,11 +87,32 @@
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
reg_emac_3v3: emac-3v3 {

21
arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
View file

@ -40,12 +40,6 @@
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
usbphy: phy@01c13400 {
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
@ -67,6 +61,21 @@
ohci1: usb@01c1c400 {
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
reg_usb1_vbus: usb1-vbus {

28
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
View file

@ -52,11 +52,39 @@
status = "okay";
};
pinctrl@01c20800 {
ir0_pins_a: ir0@0 {
/* The ir receiver is not always populated */
allwinner,pull = <1>;
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
reg_usb1_vbus: usb1-vbus {

15
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
View file

@ -91,6 +91,21 @@
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
leds {

9
arch/arm/boot/dts/sun4i-a10-pcduino.dts
View file

@ -76,6 +76,15 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupts = <0>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

34
arch/arm/boot/dts/sun4i-a10.dtsi
View file

@ -509,7 +509,7 @@
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#interrupt-cells = <2>;
#size-cells = <0>;
#gpio-cells = <3>;
@ -593,6 +593,20 @@
allwinner,drive = <0>;
allwinner,pull = <1>;
};
ir0_pins_a: ir0@0 {
allwinner,pins = "PB3","PB4";
allwinner,function = "ir0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
ir1_pins_a: ir1@0 {
allwinner,pins = "PB22","PB23";
allwinner,function = "ir1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
timer@01c20c00 {
@ -621,6 +635,24 @@
status = "disabled";
};
ir0: ir@01c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
clock-names = "apb", "ir";
interrupts = <5>;
reg = <0x01c21800 0x40>;
status = "disabled";
};
ir1: ir@01c21c00 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 7>, <&ir1_clk>;
clock-names = "apb", "ir";
interrupts = <6>;
reg = <0x01c21c00 0x40>;
status = "disabled";
};
sid: eeprom@01c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;

2
arch/arm/boot/dts/sun5i-a10s.dtsi
View file

@ -422,7 +422,7 @@
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#interrupt-cells = <2>;
#size-cells = <0>;
#gpio-cells = <3>;

2
arch/arm/boot/dts/sun5i-a13.dtsi
View file

@ -395,7 +395,7 @@
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#interrupt-cells = <2>;
#size-cells = <0>;
#gpio-cells = <3>;

119
arch/arm/boot/dts/sun6i-a31-hummingbird.dts Normal file
View file

@ -0,0 +1,119 @@
/*
* Copyright 2014 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun6i-a31.dtsi"
/include/ "sunxi-common-regulators.dtsi"
/ {
model = "Merrii A31 Hummingbird";
compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31";
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
soc@01c00000 {
mmc0: mmc@01c0f000 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
vmmc-supply = <&reg_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 0 8 0>; /* PA8 */
cd-inverted;
status = "okay";
};
usbphy: phy@01c19400 {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
ehci0: usb@01c1a000 {
status = "okay";
};
ohci0: usb@01c1a400 {
status = "okay";
};
pio: pinctrl@01c20800 {
mmc0_pins_a: mmc0@0 {
/* external pull-ups missing for some pins */
allwinner,pull = <1>;
};
mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
allwinner,pins = "PA8";
allwinner,function = "gpio_in";
allwinner,drive = <0>;
allwinner,pull = <1>;
};
usb1_vbus_pin_a: usb1_vbus_pin@0 {
allwinner,pins = "PH24";
allwinner,function = "gpio_out";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
/* pull-ups and devices require AXP221 DLDO3 */
status = "failed";
};
i2c1: i2c@01c2b000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
i2c2: i2c@01c2b400 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
gmac: ethernet@01c30000 {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_rgmii_a>;
phy = <&phy1>;
phy-mode = "rgmii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
reg_usb1_vbus: usb1-vbus {
pinctrl-0 = <&usb1_vbus_pin_a>;
gpio = <&pio 7 24 0>; /* PH24 */
status = "okay";
};
};

92
arch/arm/boot/dts/sun6i-a31.dtsi
View file

@ -23,6 +23,7 @@
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
ethernet0 = &gmac;
};
@ -281,6 +282,34 @@
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
};
/*
* The following two are dummy clocks, placeholders used in the gmac_tx
* clock. The gmac driver will choose one parent depending on the PHY
* interface mode, using clk_set_rate auto-reparenting.
* The actual TX clock rate is not controlled by the gmac_tx clock.
*/
mii_phy_tx_clk: clk@1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
gmac_int_tx_clk: clk@2 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_int_tx";
};
gmac_tx_clk: clk@01c200d0 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x01c200d0 0x4>;
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
clock-output-names = "gmac_tx";
};
};
soc@01c00000 {
@ -429,7 +458,7 @@
clocks = <&apb1_gates 5>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#interrupt-cells = <2>;
#size-cells = <0>;
#gpio-cells = <3>;
@ -467,6 +496,48 @@
allwinner,drive = <2>;
allwinner,pull = <0>;
};
gmac_pins_mii_a: gmac_mii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA8", "PA9", "PA11",
"PA12", "PA13", "PA14", "PA19",
"PA20", "PA21", "PA22", "PA23",
"PA24", "PA26", "PA27";
allwinner,function = "gmac";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
gmac_pins_gmii_a: gmac_gmii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
"PA8", "PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA15",
"PA16", "PA17", "PA18", "PA19",
"PA20", "PA21", "PA22", "PA23",
"PA24", "PA25", "PA26", "PA27";
allwinner,function = "gmac";
/*
* data lines in GMII mode run at 125MHz and
* might need a higher signal drive strength
*/
allwinner,drive = <2>;
allwinner,pull = <0>;
};
gmac_pins_rgmii_a: gmac_rgmii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA19",
"PA20", "PA25", "PA26", "PA27";
allwinner,function = "gmac";
/*
* data lines in RGMII mode use DDR mode
* and need a higher signal drive strength
*/
allwinner,drive = <3>;
allwinner,pull = <0>;
};
};
ahb1_rst: reset@01c202c0 {
@ -621,6 +692,23 @@
status = "disabled";
};
gmac: ethernet@01c30000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x01c30000 0x1054>;
interrupts = <0 82 4>;
interrupt-names = "macirq";
clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
resets = <&ahb1_rst 17>;
reset-names = "stmmaceth";
snps,pbl = <2>;
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
timer@01c60000 {
compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
reg = <0x01c60000 0x1000>;
@ -756,7 +844,7 @@
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#interrupt-cells = <2>;
#size-cells = <0>;
#gpio-cells = <3>;
};

16
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
View file

@ -66,6 +66,12 @@
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@ -76,6 +82,16 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 8>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
i2c1: i2c@01c2b000 {

16
arch/arm/boot/dts/sun7i-a20-cubietruck.dts
View file

@ -100,6 +100,12 @@
status = "okay";
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@ -110,6 +116,16 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 8>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
i2c1: i2c@01c2b000 {

22
arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
View file

@ -94,12 +94,34 @@
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 8>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
gmac: ethernet@01c50000 {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_mii_a>;

10
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
View file

@ -122,6 +122,16 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 8>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
i2c1: i2c@01c2b000 {

173
arch/arm/boot/dts/sun7i-a20-pcduino3.dts Normal file
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@ -0,0 +1,173 @@
/*
* Copyright 2014 Zoltan HERPAI
* Zoltan HERPAI <wigyori@uid0.hu>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun7i-a20.dtsi"
/include/ "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "LinkSprite pcDuino3";
compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
soc@01c00000 {
mmc0: mmc@01c0f000 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 0>; /* PH1 */
cd-inverted;
status = "okay";
};
usbphy: phy@01c13400 {
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};
ehci0: usb@01c14000 {
status = "okay";
};
ohci0: usb@01c14400 {
status = "okay";
};
ahci: sata@01c18000 {
target-supply = <&reg_ahci_5v>;
status = "okay";
};
ehci1: usb@01c1c000 {
status = "okay";
};
ohci1: usb@01c1c400 {
status = "okay";
};
pinctrl@01c20800 {
ahci_pwr_pin_a: ahci_pwr_pin@0 {
allwinner,pins = "PH2";
};
led_pins_pcduino3: led_pins@0 {
allwinner,pins = "PH15", "PH16";
allwinner,function = "gpio_out";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
key_pins_pcduino3: key_pins@0 {
allwinner,pins = "PH17", "PH18", "PH19";
allwinner,function = "gpio_in";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
ir0: ir@01c21800 {
pinctrl-names = "default";
pinctrl-0 = <&ir0_pins_a>;
status = "okay";
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
i2c0: i2c@01c2ac00 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
compatible = "x-powers,axp209";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 8>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
gmac: ethernet@01c50000 {
pinctrl-names = "default";
pinctrl-0 = <&gmac_pins_mii_a>;
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_pcduino3>;
tx {
label = "pcduino3:green:tx";
gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
};
rx {
label = "pcduino3:green:rx";
gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_pins_pcduino3>;
#address-cells = <1>;
#size-cells = <0>;
button@0 {
label = "Key Back";
linux,code = <KEY_BACK>;
gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
};
button@1 {
label = "Key Home";
linux,code = <KEY_HOME>;
gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
};
button@2 {
label = "Key Menu";
linux,code = <KEY_MENU>;
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
};
};
reg_usb1_vbus: usb1-vbus {
status = "okay";
};
reg_usb2_vbus: usb2-vbus {
status = "okay";
};
reg_ahci_5v: ahci-5v {
gpio = <&pio 7 2 0>;
status = "okay";
};
};

34
arch/arm/boot/dts/sun7i-a20.dtsi
View file

@ -586,7 +586,7 @@
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#interrupt-cells = <2>;
#size-cells = <0>;
#gpio-cells = <3>;
@ -738,6 +738,20 @@
allwinner,drive = <2>;
allwinner,pull = <0>;
};
ir0_pins_a: ir0@0 {
allwinner,pins = "PB3","PB4";
allwinner,function = "ir0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
ir1_pins_a: ir1@0 {
allwinner,pins = "PB22","PB23";
allwinner,function = "ir1";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
timer@01c20c00 {
@ -771,6 +785,24 @@
status = "disabled";
};
ir0: ir@01c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
clock-names = "apb", "ir";
interrupts = <0 5 4>;
reg = <0x01c21800 0x40>;
status = "disabled";
};
ir1: ir@01c21c00 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 7>, <&ir1_clk>;
clock-names = "apb", "ir";
interrupts = <0 6 4>;
reg = <0x01c21c00 0x40>;
status = "disabled";
};
sid: eeprom@01c23800 {
compatible = "allwinner,sun7i-a20-sid";
reg = <0x01c23800 0x200>;

30
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright 2014 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun8i-a23.dtsi"
/ {
model = "Ippo Q8H Dual Core Tablet (v5)";
compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
soc@01c00000 {
r_uart: serial@01f02800 {
status = "okay";
};
};
};

343
arch/arm/boot/dts/sun8i-a23.dtsi Normal file
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@ -0,0 +1,343 @@
/*
* Copyright 2014 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &r_uart;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
};
memory {
reg = <0x40000000 0x40000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
/* dummy clock until actually implemented */
pll6: pll6_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <600000000>;
clock-output-names = "pll6";
};
cpu: cpu_clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20050 0x4>;
/*
* PLL1 is listed twice here.
* While it looks suspicious, it's actually documented
* that way both in the datasheet and in the code from
* Allwinner.
*/
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
clock-output-names = "cpu";
};
axi: axi_clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-axi-clk";
reg = <0x01c20050 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
};
ahb1_mux: ahb1_mux_clk@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
clock-output-names = "ahb1_mux";
};
ahb1: ahb1_clk@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1_mux>;
clock-output-names = "ahb1";
};
apb1: apb1_clk@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1>;
clock-output-names = "apb1";
};
ahb1_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
"ahb1_nand", "ahb1_sdram",
"ahb1_hstimer", "ahb1_spi0",
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
"ahb1_csi", "ahb1_be", "ahb1_fe",
"ahb1_gpu", "ahb1_spinlock",
"ahb1_drc";
};
apb1_gates: clk@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_codec", "apb1_pio",
"apb1_daudio0", "apb1_daudio1";
};
apb2_mux: apb2_mux_clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
clock-output-names = "apb2_mux";
};
apb2: apb2_clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-apb2-div-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb2_mux>;
clock-output-names = "apb2";
};
apb2_gates: clk@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_uart0",
"apb2_uart1", "apb2_uart2",
"apb2_uart3", "apb2_uart4";
};
};
soc@01c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ahb1_rst: reset@01c202c0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202c0 0xc>;
};
apb1_rst: reset@01c202d0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d0 0x4>;
};
apb2_rst: reset@01c202d8 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x01c202d8 0x4>;
};
timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <0 18 4>,
<0 19 4>;
clocks = <&osc24M>;
};
wdt0: watchdog@01c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <0 25 4>;
};
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
interrupts = <0 0 4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 16>;
resets = <&apb2_rst 16>;
status = "disabled";
};
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <0 1 4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 17>;
resets = <&apb2_rst 17>;
status = "disabled";
};
uart2: serial@01c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <0 2 4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 18>;
resets = <&apb2_rst 18>;
status = "disabled";
};
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <0 3 4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 19>;
resets = <&apb2_rst 19>;
status = "disabled";
};
uart4: serial@01c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <0 4 4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb2_gates 20>;
resets = <&apb2_rst 20>;
status = "disabled";
};
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x1000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <1 9 0xf04>;
};
prcm@01f01400 {
compatible = "allwinner,sun8i-a23-prcm";
reg = <0x01f01400 0x200>;
ar100: ar100_clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&osc24M>;
clock-output-names = "ar100";
};
ahb0: ahb0_clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
clocks = <&ar100>;
clock-output-names = "ahb0";
};
apb0: apb0_clk {
compatible = "allwinner,sun8i-a23-apb0-clk";
#clock-cells = <0>;
clocks = <&ahb0>;
clock-output-names = "apb0";
};
apb0_gates: apb0_gates_clk {
compatible = "allwinner,sun8i-a23-apb0-gates-clk";
#clock-cells = <1>;
clocks = <&apb0>;
clock-output-names = "apb0_pio", "apb0_timer",
"apb0_rsb", "apb0_uart",
"apb0_i2c";
};
apb0_rst: apb0_rst {
compatible = "allwinner,sun6i-a31-clock-reset";
#reset-cells = <1>;
};
};
r_uart: serial@01f02800 {
compatible = "snps,dw-apb-uart";
reg = <0x01f02800 0x400>;
interrupts = <0 38 4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb0_gates 4>;
resets = <&apb0_rst 4>;
status = "disabled";
};
};
};