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mmc: core: Add at least 3 mclk cycle delay before next command after ACMD41

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As per design, internal CRC error flag will be cleared only after 3 MCLK
once clear command issued. Since the MCLK will be running at 400KHz during
initialization, it will take max of 7.5us (2.5us *3 = 7.5us) to clear
the status. If the CMD_CRC_CHECK_EN bit is enabled before the source is
cleared, CRC INTR bit will be set in the 17th bit of INTR status register.
Because the response of ACMD41 in sd and CMD1 in mmc are R3 response that
don't have CRC field, so it is expected to give next command after at least
3 MCLK periods.

Change-Id: I31b52a767f2212d33cab15251ab5b37a04b25618
Signed-off-by: Jun Li <liju@codeaurora.org>
This commit is contained in:
Jun Li 2020-07-13 09:17:41 +08:00 committed by Sarthak Garg
parent 8fd8b33f9f
commit 197ddb978d
2 changed files with 24 additions and 0 deletions
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12
drivers/mmc/core/mmc_ops.c
View file

@ -205,6 +205,18 @@ int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
if (rocr && !mmc_host_is_spi(host))
*rocr = cmd.resp[0];
/*
* As per design, internal CRC error flag will be cleared after 3
* MCLK once clear command issued. Since the MCLK will be running
* at 400KHz during initialization, design is taking max of 7.5us
* to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled
* before the source is cleared, CRC INTR bit will be set in the 17th
* bit of INTR status register. So it expected to issue the next
* command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay.
*/
if (!err)
udelay(8);
return err;
}

12
drivers/mmc/core/sd_ops.c
View file

@ -180,6 +180,18 @@ int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
if (rocr && !mmc_host_is_spi(host))
*rocr = cmd.resp[0];
/*
* As per design, internal CRC error flag will be cleared after 3
* MCLK once clear command issued. Since the MCLK will be running
* at 400KHz during initialization, design is taking max of 7.5us
* to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled
* before the source is cleared, CRC INTR bit will be set in the 17th
* bit of INTR status register. So it expected to issue the next
* command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay.
*/
if (!err)
udelay(8);
return err;
}