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drm/radeon: separate vblank and pflip crtc handling

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Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2014-05-27 16:49:21 +02:00 committed by Alex Deucher
parent 157fa14dc4
commit 1a0e791841
8 changed files with 56 additions and 26 deletions
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12
drivers/gpu/drm/radeon/cik.c
View file

@ -7314,7 +7314,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[0])) if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 0); radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n"); DRM_DEBUG("IH: D1 vblank\n");
} }
@ -7340,7 +7340,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[1])) if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 1); radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n"); DRM_DEBUG("IH: D2 vblank\n");
} }
@ -7366,7 +7366,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[2])) if (atomic_read(&rdev->irq.pflip[2]))
radeon_crtc_handle_flip(rdev, 2); radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n"); DRM_DEBUG("IH: D3 vblank\n");
} }
@ -7392,7 +7392,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[3])) if (atomic_read(&rdev->irq.pflip[3]))
radeon_crtc_handle_flip(rdev, 3); radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n"); DRM_DEBUG("IH: D4 vblank\n");
} }
@ -7418,7 +7418,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[4])) if (atomic_read(&rdev->irq.pflip[4]))
radeon_crtc_handle_flip(rdev, 4); radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n"); DRM_DEBUG("IH: D5 vblank\n");
} }
@ -7444,7 +7444,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[5])) if (atomic_read(&rdev->irq.pflip[5]))
radeon_crtc_handle_flip(rdev, 5); radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n"); DRM_DEBUG("IH: D6 vblank\n");
} }

12
drivers/gpu/drm/radeon/evergreen.c
View file

@ -4789,7 +4789,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[0])) if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 0); radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n"); DRM_DEBUG("IH: D1 vblank\n");
} }
@ -4815,7 +4815,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[1])) if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 1); radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n"); DRM_DEBUG("IH: D2 vblank\n");
} }
@ -4841,7 +4841,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[2])) if (atomic_read(&rdev->irq.pflip[2]))
radeon_crtc_handle_flip(rdev, 2); radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n"); DRM_DEBUG("IH: D3 vblank\n");
} }
@ -4867,7 +4867,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[3])) if (atomic_read(&rdev->irq.pflip[3]))
radeon_crtc_handle_flip(rdev, 3); radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n"); DRM_DEBUG("IH: D4 vblank\n");
} }
@ -4893,7 +4893,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[4])) if (atomic_read(&rdev->irq.pflip[4]))
radeon_crtc_handle_flip(rdev, 4); radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n"); DRM_DEBUG("IH: D5 vblank\n");
} }
@ -4919,7 +4919,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[5])) if (atomic_read(&rdev->irq.pflip[5]))
radeon_crtc_handle_flip(rdev, 5); radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n"); DRM_DEBUG("IH: D6 vblank\n");
} }

4
drivers/gpu/drm/radeon/r100.c
View file

@ -779,7 +779,7 @@ int r100_irq_process(struct radeon_device *rdev)
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[0])) if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 0); radeon_crtc_handle_vblank(rdev, 0);
} }
if (status & RADEON_CRTC2_VBLANK_STAT) { if (status & RADEON_CRTC2_VBLANK_STAT) {
if (rdev->irq.crtc_vblank_int[1]) { if (rdev->irq.crtc_vblank_int[1]) {
@ -788,7 +788,7 @@ int r100_irq_process(struct radeon_device *rdev)
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[1])) if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 1); radeon_crtc_handle_vblank(rdev, 1);
} }
if (status & RADEON_FP_DETECT_STAT) { if (status & RADEON_FP_DETECT_STAT) {
queue_hotplug = true; queue_hotplug = true;

4
drivers/gpu/drm/radeon/r600.c
View file

@ -3876,7 +3876,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[0])) if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 0); radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n"); DRM_DEBUG("IH: D1 vblank\n");
} }
@ -3902,7 +3902,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[1])) if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 1); radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n"); DRM_DEBUG("IH: D2 vblank\n");
} }

33
drivers/gpu/drm/radeon/radeon_display.c
View file

@ -276,7 +276,7 @@ static void radeon_unpin_work_func(struct work_struct *__work)
kfree(work); kfree(work);
} }
void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
{ {
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
struct radeon_unpin_work *work; struct radeon_unpin_work *work;
@ -302,7 +302,6 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
* completion routine. * completion routine.
*/ */
update_pending = 0; update_pending = 0;
radeon_crtc->deferred_flip_completion = 0;
} }
/* Has the pageflip already completed in crtc, or is it certain /* Has the pageflip already completed in crtc, or is it certain
@ -330,10 +329,40 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
radeon_crtc->deferred_flip_completion = 1; radeon_crtc->deferred_flip_completion = 1;
spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
return; return;
} else {
spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
radeon_crtc_handle_flip(rdev, crtc_id);
}
}
/**
* radeon_crtc_handle_flip - page flip completed
*
* @rdev: radeon device pointer
* @crtc_id: crtc number this event is for
*
* Called when we are sure that a page flip for this crtc is completed.
*/
void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
{
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
struct radeon_unpin_work *work;
unsigned long flags;
/* this can happen at init */
if (radeon_crtc == NULL)
return;
spin_lock_irqsave(&rdev->ddev->event_lock, flags);
work = radeon_crtc->unpin_work;
if (work == NULL) {
spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
return;
} }
/* Pageflip (will be) certainly completed in this vblank. Clean up. */ /* Pageflip (will be) certainly completed in this vblank. Clean up. */
radeon_crtc->unpin_work = NULL; radeon_crtc->unpin_work = NULL;
radeon_crtc->deferred_flip_completion = 0;
/* wakeup userspace */ /* wakeup userspace */
if (work->event) if (work->event)

1
drivers/gpu/drm/radeon/radeon_mode.h
View file

@ -907,6 +907,7 @@ bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
void radeon_fb_output_poll_changed(struct radeon_device *rdev); void radeon_fb_output_poll_changed(struct radeon_device *rdev);
void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);

4
drivers/gpu/drm/radeon/rs600.c
View file

@ -781,7 +781,7 @@ int rs600_irq_process(struct radeon_device *rdev)
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[0])) if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 0); radeon_crtc_handle_vblank(rdev, 0);
} }
if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
if (rdev->irq.crtc_vblank_int[1]) { if (rdev->irq.crtc_vblank_int[1]) {
@ -790,7 +790,7 @@ int rs600_irq_process(struct radeon_device *rdev)
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[1])) if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 1); radeon_crtc_handle_vblank(rdev, 1);
} }
if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
queue_hotplug = true; queue_hotplug = true;

12
drivers/gpu/drm/radeon/si.c
View file

@ -6150,7 +6150,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[0])) if (atomic_read(&rdev->irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 0); radeon_crtc_handle_vblank(rdev, 0);
rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n"); DRM_DEBUG("IH: D1 vblank\n");
} }
@ -6176,7 +6176,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[1])) if (atomic_read(&rdev->irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 1); radeon_crtc_handle_vblank(rdev, 1);
rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D2 vblank\n"); DRM_DEBUG("IH: D2 vblank\n");
} }
@ -6202,7 +6202,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[2])) if (atomic_read(&rdev->irq.pflip[2]))
radeon_crtc_handle_flip(rdev, 2); radeon_crtc_handle_vblank(rdev, 2);
rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D3 vblank\n"); DRM_DEBUG("IH: D3 vblank\n");
} }
@ -6228,7 +6228,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[3])) if (atomic_read(&rdev->irq.pflip[3]))
radeon_crtc_handle_flip(rdev, 3); radeon_crtc_handle_vblank(rdev, 3);
rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D4 vblank\n"); DRM_DEBUG("IH: D4 vblank\n");
} }
@ -6254,7 +6254,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[4])) if (atomic_read(&rdev->irq.pflip[4]))
radeon_crtc_handle_flip(rdev, 4); radeon_crtc_handle_vblank(rdev, 4);
rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D5 vblank\n"); DRM_DEBUG("IH: D5 vblank\n");
} }
@ -6280,7 +6280,7 @@ restart_ih:
wake_up(&rdev->irq.vblank_queue); wake_up(&rdev->irq.vblank_queue);
} }
if (atomic_read(&rdev->irq.pflip[5])) if (atomic_read(&rdev->irq.pflip[5]))
radeon_crtc_handle_flip(rdev, 5); radeon_crtc_handle_vblank(rdev, 5);
rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D6 vblank\n"); DRM_DEBUG("IH: D6 vblank\n");
} }