mvebu watchdog driver changes for v3.15
- orion watchdog - cleanup and extend driver to support Armada 370 and Armada XP Depends: - tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx) - both are based on v3.14-rc1 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJTCEm3AAoJEP45WPkGe8Zn46EP/iII5DaCXy6LES+k5W7Tp3H8 dFNgKEq/1ifoMFwhehhfB2ySSBwDxNpr1fAIR9qyQLLqamjDtUVpiYBqbyhBwPGz 0bIJz9W65ibb4f2xEtQTS0DroPlH4EbfolpEqjrJ+zkep316I5KRMY9tzyJoure9 W+jU9gEo5rnfq+mCGP2+ZlCoO7QAn7/DUGySpe/oEKNQqWbARHutFUy9aIY94X2f evo4C4Suei4B+SVLL8+9F6taodwfSuGUV8m75wQeNNyEHr3xvS8MZvDkwYaGGZJe VNhvHTUrgU16PaOcq4lZ8Zk7S8ZWt80Y4cu0V/AWuT0oHFyekRGZyHtus/YjxY6G TyJjlC8PF8AvlH3E4D6/wAOISdC3sCEYzeFjeNeoyX1RjvZogsC+nCDknGKImBHX lo63MC8CSBgPTb4rgj4pbFnnpN4fNO1ppacawmaeIPgX3CvqOJtB1GitD0CMf64w oxd9mYWRXjfQzObfMyRlq5WywHN2Hmob5R5C7xR9lwcK5iiq2ibtBb7pGVeVEsYd Sg/3A6IKJs1DmLiA7KUiR/jmIJrdBEzGRWfnLgqBlAs+5kTFj6OClGewBg7Lu673 A+3KjwgCcYzesXdV+88bwtAucA9DoS0gwnarhDCFNn/pDIAQpfq8UIKMxuMqz1Mj ep+ZLbXY1T1yNeU1oXN4 =3VWF -----END PGP SIGNATURE----- Merge tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu into next/drivers mvebu watchdog driver changes for v3.15 - orion watchdog - cleanup and extend driver to support Armada 370 and Armada XP Depends: - tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx) - both are based on v3.14-rc1 * tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu: watchdog: orion: Enable the build on ARCH_MVEBU watchdog: orion: Add support for Armada 370 and Armada XP SoC watchdog: orion: Add per-compatible watchdog start implementation watchdog: orion: Add per-compatible clock initialization watchdog: orion: Introduce per-compatible of_device_id data watchdog: orion: Introduce an orion_watchdog device structure watchdog: orion: Remove unneeded BRIDGE_CAUSE clear watchdog: orion: Make RSTOUT register a separate resource watchdog: orion: Handle the interrupt so it's properly acked watchdog: orion: Make sure the watchdog is initially stopped watchdog: orion: Remove unused macros watchdog: orion: Use atomic access for shared registers watchdog: orion: Add clock error handling Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
1e7bdf82ab
8 changed files with 330 additions and 94 deletions
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@ -3,17 +3,24 @@
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||||||
Required Properties:
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Required Properties:
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||||||
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- Compatibility : "marvell,orion-wdt"
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- Compatibility : "marvell,orion-wdt"
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- reg : Address of the timer registers
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"marvell,armada-370-wdt"
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"marvell,armada-xp-wdt"
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- reg : Should contain two entries: first one with the
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timer control address, second one with the
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rstout enable address.
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Optional properties:
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Optional properties:
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- interrupts : Contains the IRQ for watchdog expiration
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- timeout-sec : Contains the watchdog timeout in seconds
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- timeout-sec : Contains the watchdog timeout in seconds
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Example:
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Example:
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wdt@20300 {
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wdt@20300 {
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compatible = "marvell,orion-wdt";
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compatible = "marvell,orion-wdt";
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reg = <0x20300 0x28>;
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reg = <0x20300 0x28>, <0x20108 0x4>;
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interrupts = <3>;
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timeout-sec = <10>;
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timeout-sec = <10>;
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status = "okay";
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status = "okay";
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};
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};
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@ -21,6 +21,7 @@
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#define CPU_CTRL_PCIE1_LINK 0x00000008
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#define CPU_CTRL_PCIE1_LINK 0x00000008
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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@ -21,6 +21,7 @@
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#define CPU_RESET 0x00000002
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#define CPU_RESET 0x00000002
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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@ -15,6 +15,7 @@
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#define L2_WRITETHROUGH 0x00020000
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#define L2_WRITETHROUGH 0x00020000
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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@ -18,6 +18,7 @@
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#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
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#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
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#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
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#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
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#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
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#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
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#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
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@ -595,14 +595,16 @@ void __init orion_spi_1_init(unsigned long mapbase)
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/*****************************************************************************
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/*****************************************************************************
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* Watchdog
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* Watchdog
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****************************************************************************/
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****************************************************************************/
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static struct resource orion_wdt_resource =
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static struct resource orion_wdt_resource[] = {
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DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x28);
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DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
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DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
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};
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static struct platform_device orion_wdt_device = {
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static struct platform_device orion_wdt_device = {
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.name = "orion_wdt",
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.name = "orion_wdt",
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.id = -1,
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.id = -1,
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.num_resources = 1,
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.num_resources = ARRAY_SIZE(orion_wdt_resource),
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.resource = &orion_wdt_resource,
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.resource = orion_wdt_resource,
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};
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};
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void __init orion_wdt_init(void)
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void __init orion_wdt_init(void)
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@ -292,7 +292,7 @@ config DAVINCI_WATCHDOG
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config ORION_WATCHDOG
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config ORION_WATCHDOG
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tristate "Orion watchdog"
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tristate "Orion watchdog"
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depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE
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depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE || ARCH_MVEBU
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select WATCHDOG_CORE
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select WATCHDOG_CORE
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help
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help
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Say Y here if to include support for the watchdog timer
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Say Y here if to include support for the watchdog timer
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@ -19,101 +19,204 @@
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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#include <linux/watchdog.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <mach/bridge-regs.h>
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#include <linux/of_device.h>
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/* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */
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#define ORION_RSTOUT_MASK_OFFSET 0x20108
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/* Internal registers can be configured at any 1 MiB aligned address */
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#define INTERNAL_REGS_MASK ~(SZ_1M - 1)
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/*
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/*
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* Watchdog timer block registers.
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* Watchdog timer block registers.
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*/
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*/
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#define TIMER_CTRL 0x0000
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#define TIMER_CTRL 0x0000
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#define WDT_EN 0x0010
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#define TIMER_A370_STATUS 0x04
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#define WDT_VAL 0x0024
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#define WDT_MAX_CYCLE_COUNT 0xffffffff
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#define WDT_MAX_CYCLE_COUNT 0xffffffff
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#define WDT_IN_USE 0
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#define WDT_OK_TO_CLOSE 1
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#define WDT_RESET_OUT_EN BIT(1)
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#define WDT_A370_RATIO_MASK(v) ((v) << 16)
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#define WDT_INT_REQ BIT(3)
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#define WDT_A370_RATIO_SHIFT 5
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#define WDT_A370_RATIO (1 << WDT_A370_RATIO_SHIFT)
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#define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
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#define WDT_A370_EXPIRED BIT(31)
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static bool nowayout = WATCHDOG_NOWAYOUT;
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static bool nowayout = WATCHDOG_NOWAYOUT;
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static int heartbeat = -1; /* module parameter (seconds) */
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static int heartbeat = -1; /* module parameter (seconds) */
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static unsigned int wdt_max_duration; /* (seconds) */
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static struct clk *clk;
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struct orion_watchdog;
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static unsigned int wdt_tclk;
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static void __iomem *wdt_reg;
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struct orion_watchdog_data {
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static DEFINE_SPINLOCK(wdt_lock);
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int wdt_counter_offset;
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int wdt_enable_bit;
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int rstout_enable_bit;
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int (*clock_init)(struct platform_device *,
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struct orion_watchdog *);
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int (*start)(struct watchdog_device *);
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};
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struct orion_watchdog {
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struct watchdog_device wdt;
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void __iomem *reg;
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void __iomem *rstout;
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unsigned long clk_rate;
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struct clk *clk;
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const struct orion_watchdog_data *data;
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};
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static int orion_wdt_clock_init(struct platform_device *pdev,
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struct orion_watchdog *dev)
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{
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int ret;
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dev->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(dev->clk))
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return PTR_ERR(dev->clk);
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ret = clk_prepare_enable(dev->clk);
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if (ret) {
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clk_put(dev->clk);
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return ret;
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}
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dev->clk_rate = clk_get_rate(dev->clk);
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return 0;
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}
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static int armada370_wdt_clock_init(struct platform_device *pdev,
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struct orion_watchdog *dev)
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{
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int ret;
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dev->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(dev->clk))
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return PTR_ERR(dev->clk);
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ret = clk_prepare_enable(dev->clk);
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if (ret) {
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clk_put(dev->clk);
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return ret;
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}
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/* Setup watchdog input clock */
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atomic_io_modify(dev->reg + TIMER_CTRL,
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WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
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WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
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dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
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return 0;
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}
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static int armadaxp_wdt_clock_init(struct platform_device *pdev,
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struct orion_watchdog *dev)
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{
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int ret;
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dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
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if (IS_ERR(dev->clk))
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return PTR_ERR(dev->clk);
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ret = clk_prepare_enable(dev->clk);
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if (ret) {
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clk_put(dev->clk);
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return ret;
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}
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/* Enable the fixed watchdog clock input */
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atomic_io_modify(dev->reg + TIMER_CTRL,
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WDT_AXP_FIXED_ENABLE_BIT,
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WDT_AXP_FIXED_ENABLE_BIT);
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dev->clk_rate = clk_get_rate(dev->clk);
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return 0;
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}
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static int orion_wdt_ping(struct watchdog_device *wdt_dev)
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static int orion_wdt_ping(struct watchdog_device *wdt_dev)
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{
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{
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spin_lock(&wdt_lock);
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struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
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/* Reload watchdog duration */
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/* Reload watchdog duration */
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writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL);
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writel(dev->clk_rate * wdt_dev->timeout,
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dev->reg + dev->data->wdt_counter_offset);
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return 0;
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}
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static int armada370_start(struct watchdog_device *wdt_dev)
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{
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struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
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/* Set watchdog duration */
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writel(dev->clk_rate * wdt_dev->timeout,
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dev->reg + dev->data->wdt_counter_offset);
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/* Clear the watchdog expiration bit */
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atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
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/* Enable watchdog timer */
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atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
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dev->data->wdt_enable_bit);
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atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit,
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dev->data->rstout_enable_bit);
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return 0;
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}
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static int orion_start(struct watchdog_device *wdt_dev)
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{
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struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
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/* Set watchdog duration */
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writel(dev->clk_rate * wdt_dev->timeout,
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dev->reg + dev->data->wdt_counter_offset);
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/* Enable watchdog timer */
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atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
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dev->data->wdt_enable_bit);
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/* Enable reset on watchdog */
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atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit,
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dev->data->rstout_enable_bit);
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spin_unlock(&wdt_lock);
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|
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return 0;
|
return 0;
|
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}
|
}
|
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|
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static int orion_wdt_start(struct watchdog_device *wdt_dev)
|
static int orion_wdt_start(struct watchdog_device *wdt_dev)
|
||||||
{
|
{
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u32 reg;
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struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
|
||||||
|
|
||||||
spin_lock(&wdt_lock);
|
/* There are some per-SoC quirks to handle */
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|
return dev->data->start(wdt_dev);
|
||||||
/* Set watchdog duration */
|
|
||||||
writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL);
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|
||||||
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|
||||||
/* Clear watchdog timer interrupt */
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|
||||||
writel(~WDT_INT_REQ, BRIDGE_CAUSE);
|
|
||||||
|
|
||||||
/* Enable watchdog timer */
|
|
||||||
reg = readl(wdt_reg + TIMER_CTRL);
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|
||||||
reg |= WDT_EN;
|
|
||||||
writel(reg, wdt_reg + TIMER_CTRL);
|
|
||||||
|
|
||||||
/* Enable reset on watchdog */
|
|
||||||
reg = readl(RSTOUTn_MASK);
|
|
||||||
reg |= WDT_RESET_OUT_EN;
|
|
||||||
writel(reg, RSTOUTn_MASK);
|
|
||||||
|
|
||||||
spin_unlock(&wdt_lock);
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|
||||||
return 0;
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|
||||||
}
|
}
|
||||||
|
|
||||||
static int orion_wdt_stop(struct watchdog_device *wdt_dev)
|
static int orion_wdt_stop(struct watchdog_device *wdt_dev)
|
||||||
{
|
{
|
||||||
u32 reg;
|
struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
|
||||||
|
|
||||||
spin_lock(&wdt_lock);
|
|
||||||
|
|
||||||
/* Disable reset on watchdog */
|
/* Disable reset on watchdog */
|
||||||
reg = readl(RSTOUTn_MASK);
|
atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0);
|
||||||
reg &= ~WDT_RESET_OUT_EN;
|
|
||||||
writel(reg, RSTOUTn_MASK);
|
|
||||||
|
|
||||||
/* Disable watchdog timer */
|
/* Disable watchdog timer */
|
||||||
reg = readl(wdt_reg + TIMER_CTRL);
|
atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
|
||||||
reg &= ~WDT_EN;
|
|
||||||
writel(reg, wdt_reg + TIMER_CTRL);
|
|
||||||
|
|
||||||
spin_unlock(&wdt_lock);
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int orion_wdt_enabled(struct orion_watchdog *dev)
|
||||||
|
{
|
||||||
|
bool enabled, running;
|
||||||
|
|
||||||
|
enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
|
||||||
|
running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
|
||||||
|
|
||||||
|
return enabled && running;
|
||||||
|
}
|
||||||
|
|
||||||
static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev)
|
static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev)
|
||||||
{
|
{
|
||||||
unsigned int time_left;
|
struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
|
||||||
|
return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate;
|
||||||
spin_lock(&wdt_lock);
|
|
||||||
time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk;
|
|
||||||
spin_unlock(&wdt_lock);
|
|
||||||
|
|
||||||
return time_left;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev,
|
static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev,
|
||||||
|
@ -137,68 +240,188 @@ static const struct watchdog_ops orion_wdt_ops = {
|
||||||
.get_timeleft = orion_wdt_get_timeleft,
|
.get_timeleft = orion_wdt_get_timeleft,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct watchdog_device orion_wdt = {
|
static irqreturn_t orion_wdt_irq(int irq, void *devid)
|
||||||
.info = &orion_wdt_info,
|
{
|
||||||
.ops = &orion_wdt_ops,
|
panic("Watchdog Timeout");
|
||||||
.min_timeout = 1,
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The original devicetree binding for this driver specified only
|
||||||
|
* one memory resource, so in order to keep DT backwards compatibility
|
||||||
|
* we try to fallback to a hardcoded register address, if the resource
|
||||||
|
* is missing from the devicetree.
|
||||||
|
*/
|
||||||
|
static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev,
|
||||||
|
phys_addr_t internal_regs)
|
||||||
|
{
|
||||||
|
struct resource *res;
|
||||||
|
phys_addr_t rstout;
|
||||||
|
|
||||||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||||
|
if (res)
|
||||||
|
return devm_ioremap(&pdev->dev, res->start,
|
||||||
|
resource_size(res));
|
||||||
|
|
||||||
|
/* This workaround works only for "orion-wdt", DT-enabled */
|
||||||
|
if (!of_device_is_compatible(pdev->dev.of_node, "marvell,orion-wdt"))
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET;
|
||||||
|
|
||||||
|
WARN(1, FW_BUG "falling back to harcoded RSTOUT reg 0x%x\n", rstout);
|
||||||
|
return devm_ioremap(&pdev->dev, rstout, 0x4);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct orion_watchdog_data orion_data = {
|
||||||
|
.rstout_enable_bit = BIT(1),
|
||||||
|
.wdt_enable_bit = BIT(4),
|
||||||
|
.wdt_counter_offset = 0x24,
|
||||||
|
.clock_init = orion_wdt_clock_init,
|
||||||
|
.start = orion_start,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct orion_watchdog_data armada370_data = {
|
||||||
|
.rstout_enable_bit = BIT(8),
|
||||||
|
.wdt_enable_bit = BIT(8),
|
||||||
|
.wdt_counter_offset = 0x34,
|
||||||
|
.clock_init = armada370_wdt_clock_init,
|
||||||
|
.start = armada370_start,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct orion_watchdog_data armadaxp_data = {
|
||||||
|
.rstout_enable_bit = BIT(8),
|
||||||
|
.wdt_enable_bit = BIT(8),
|
||||||
|
.wdt_counter_offset = 0x34,
|
||||||
|
.clock_init = armadaxp_wdt_clock_init,
|
||||||
|
.start = armada370_start,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct of_device_id orion_wdt_of_match_table[] = {
|
||||||
|
{
|
||||||
|
.compatible = "marvell,orion-wdt",
|
||||||
|
.data = &orion_data,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.compatible = "marvell,armada-370-wdt",
|
||||||
|
.data = &armada370_data,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.compatible = "marvell,armada-xp-wdt",
|
||||||
|
.data = &armadaxp_data,
|
||||||
|
},
|
||||||
|
{},
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table);
|
||||||
|
|
||||||
static int orion_wdt_probe(struct platform_device *pdev)
|
static int orion_wdt_probe(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
|
struct orion_watchdog *dev;
|
||||||
|
const struct of_device_id *match;
|
||||||
|
unsigned int wdt_max_duration; /* (seconds) */
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
int ret;
|
int ret, irq;
|
||||||
|
|
||||||
clk = devm_clk_get(&pdev->dev, NULL);
|
dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog),
|
||||||
if (IS_ERR(clk)) {
|
GFP_KERNEL);
|
||||||
dev_err(&pdev->dev, "Orion Watchdog missing clock\n");
|
if (!dev)
|
||||||
return -ENODEV;
|
return -ENOMEM;
|
||||||
}
|
|
||||||
clk_prepare_enable(clk);
|
match = of_match_device(orion_wdt_of_match_table, &pdev->dev);
|
||||||
wdt_tclk = clk_get_rate(clk);
|
if (!match)
|
||||||
|
/* Default legacy match */
|
||||||
|
match = &orion_wdt_of_match_table[0];
|
||||||
|
|
||||||
|
dev->wdt.info = &orion_wdt_info;
|
||||||
|
dev->wdt.ops = &orion_wdt_ops;
|
||||||
|
dev->wdt.min_timeout = 1;
|
||||||
|
dev->data = match->data;
|
||||||
|
|
||||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
if (!res)
|
if (!res)
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
wdt_reg = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
|
||||||
if (!wdt_reg)
|
dev->reg = devm_ioremap(&pdev->dev, res->start,
|
||||||
|
resource_size(res));
|
||||||
|
if (!dev->reg)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
wdt_max_duration = WDT_MAX_CYCLE_COUNT / wdt_tclk;
|
dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start &
|
||||||
|
INTERNAL_REGS_MASK);
|
||||||
|
if (!dev->rstout)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
orion_wdt.timeout = wdt_max_duration;
|
ret = dev->data->clock_init(pdev, dev);
|
||||||
orion_wdt.max_timeout = wdt_max_duration;
|
|
||||||
watchdog_init_timeout(&orion_wdt, heartbeat, &pdev->dev);
|
|
||||||
|
|
||||||
watchdog_set_nowayout(&orion_wdt, nowayout);
|
|
||||||
ret = watchdog_register_device(&orion_wdt);
|
|
||||||
if (ret) {
|
if (ret) {
|
||||||
clk_disable_unprepare(clk);
|
dev_err(&pdev->dev, "cannot initialize clock\n");
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate;
|
||||||
|
|
||||||
|
dev->wdt.timeout = wdt_max_duration;
|
||||||
|
dev->wdt.max_timeout = wdt_max_duration;
|
||||||
|
watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev);
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, &dev->wdt);
|
||||||
|
watchdog_set_drvdata(&dev->wdt, dev);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Let's make sure the watchdog is fully stopped, unless it's
|
||||||
|
* explicitly enabled. This may be the case if the module was
|
||||||
|
* removed and re-insterted, or if the bootloader explicitly
|
||||||
|
* set a running watchdog before booting the kernel.
|
||||||
|
*/
|
||||||
|
if (!orion_wdt_enabled(dev))
|
||||||
|
orion_wdt_stop(&dev->wdt);
|
||||||
|
|
||||||
|
/* Request the IRQ only after the watchdog is disabled */
|
||||||
|
irq = platform_get_irq(pdev, 0);
|
||||||
|
if (irq > 0) {
|
||||||
|
/*
|
||||||
|
* Not all supported platforms specify an interrupt for the
|
||||||
|
* watchdog, so let's make it optional.
|
||||||
|
*/
|
||||||
|
ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0,
|
||||||
|
pdev->name, dev);
|
||||||
|
if (ret < 0) {
|
||||||
|
dev_err(&pdev->dev, "failed to request IRQ\n");
|
||||||
|
goto disable_clk;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
watchdog_set_nowayout(&dev->wdt, nowayout);
|
||||||
|
ret = watchdog_register_device(&dev->wdt);
|
||||||
|
if (ret)
|
||||||
|
goto disable_clk;
|
||||||
|
|
||||||
pr_info("Initial timeout %d sec%s\n",
|
pr_info("Initial timeout %d sec%s\n",
|
||||||
orion_wdt.timeout, nowayout ? ", nowayout" : "");
|
dev->wdt.timeout, nowayout ? ", nowayout" : "");
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
|
disable_clk:
|
||||||
|
clk_disable_unprepare(dev->clk);
|
||||||
|
clk_put(dev->clk);
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int orion_wdt_remove(struct platform_device *pdev)
|
static int orion_wdt_remove(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
watchdog_unregister_device(&orion_wdt);
|
struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
|
||||||
clk_disable_unprepare(clk);
|
struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
|
||||||
|
|
||||||
|
watchdog_unregister_device(wdt_dev);
|
||||||
|
clk_disable_unprepare(dev->clk);
|
||||||
|
clk_put(dev->clk);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void orion_wdt_shutdown(struct platform_device *pdev)
|
static void orion_wdt_shutdown(struct platform_device *pdev)
|
||||||
{
|
{
|
||||||
orion_wdt_stop(&orion_wdt);
|
struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
|
||||||
|
orion_wdt_stop(wdt_dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct of_device_id orion_wdt_of_match_table[] = {
|
|
||||||
{ .compatible = "marvell,orion-wdt", },
|
|
||||||
{},
|
|
||||||
};
|
|
||||||
MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table);
|
|
||||||
|
|
||||||
static struct platform_driver orion_wdt_driver = {
|
static struct platform_driver orion_wdt_driver = {
|
||||||
.probe = orion_wdt_probe,
|
.probe = orion_wdt_probe,
|
||||||
.remove = orion_wdt_remove,
|
.remove = orion_wdt_remove,
|
||||||
|
|
Loading…
Reference in a new issue