pinctrl: sirf: switch to using allocated state container
This rewrites the SIRF pinctrl driver to allocate a state container for the GPIO chip, just as is done for the pin controller, and use the gpiochip_add_pin_range() to add the range from the gpiochip side rather than adding the range from the pinctrl side. All resulting changes are done in order to pass around a state container rather than refer to a static global object. Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
ca6c55189a
commit
294d1351ff
1 changed files with 120 additions and 92 deletions
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@ -42,7 +42,6 @@ struct sirfsoc_gpio_chip {
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struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
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};
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static struct sirfsoc_gpio_chip sgpio_chip;
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static DEFINE_SPINLOCK(sgpio_lock);
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static struct sirfsoc_pin_group *sirfsoc_pin_groups;
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@ -255,17 +254,6 @@ static struct pinctrl_desc sirfsoc_pinmux_desc = {
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.owner = THIS_MODULE,
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};
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/*
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* Todo: bind irq_chip to every pinctrl_gpio_range
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*/
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static struct pinctrl_gpio_range sirfsoc_gpio_ranges = {
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.name = "sirfsoc-gpio*",
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.id = 0,
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.base = 0,
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.pin_base = 0,
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.npins = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS,
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};
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static void __iomem *sirfsoc_rsc_of_iomap(void)
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{
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const struct of_device_id rsc_ids[] = {
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@ -289,9 +277,6 @@ static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
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if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
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return -EINVAL;
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if (gc != &sgpio_chip.chip.gc)
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return -EINVAL;
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if (flags)
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*flags = gpiospec->args[1];
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@ -354,9 +339,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
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goto out_no_pmx;
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}
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sirfsoc_gpio_ranges.gc = &sgpio_chip.chip.gc;
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pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges);
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dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
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return 0;
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@ -441,20 +423,28 @@ static int __init sirfsoc_pinmux_init(void)
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}
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arch_initcall(sirfsoc_pinmux_init);
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static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
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static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc)
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{
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return &sgpio_chip.sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
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return container_of(gc, struct sirfsoc_gpio_chip, chip.gc);
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}
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static inline int sirfsoc_gpio_to_bankoff(unsigned int gpio)
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static inline struct sirfsoc_gpio_bank *
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sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
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{
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return gpio % SIRFSOC_GPIO_BANK_SIZE;
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return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
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}
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static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
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{
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return offset % SIRFSOC_GPIO_BANK_SIZE;
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}
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static void sirfsoc_gpio_irq_ack(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
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int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
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u32 val, offset;
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unsigned long flags;
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@ -462,14 +452,16 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(sgpio_chip.chip.regs + offset);
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val = readl(sgpio->chip.regs + offset);
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writel(val, sgpio_chip.chip.regs + offset);
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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}
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static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
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static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
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struct sirfsoc_gpio_bank *bank,
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int idx)
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{
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u32 val, offset;
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unsigned long flags;
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@ -478,25 +470,29 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(sgpio_chip.chip.regs + offset);
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val = readl(sgpio->chip.regs + offset);
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val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
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writel(val, sgpio_chip.chip.regs + offset);
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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}
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static void sirfsoc_gpio_irq_mask(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
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__sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
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__sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
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}
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static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
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int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
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u32 val, offset;
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unsigned long flags;
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@ -504,18 +500,20 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(sgpio_chip.chip.regs + offset);
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val = readl(sgpio->chip.regs + offset);
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val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
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val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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writel(val, sgpio_chip.chip.regs + offset);
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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}
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static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(d->hwirq);
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int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
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int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
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u32 val, offset;
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unsigned long flags;
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@ -523,7 +521,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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spin_lock_irqsave(&sgpio_lock, flags);
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val = readl(sgpio_chip.chip.regs + offset);
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val = readl(sgpio->chip.regs + offset);
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val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
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switch (type) {
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@ -551,7 +549,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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break;
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}
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writel(val, sgpio_chip.chip.regs + offset);
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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@ -568,6 +566,8 @@ static struct irq_chip sirfsoc_irq_chip = {
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static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
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struct sirfsoc_gpio_bank *bank;
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u32 status, ctrl;
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int idx = 0;
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@ -583,7 +583,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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status = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
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status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
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if (!status) {
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printk(KERN_WARNING
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"%s: gpio id %d status %#x no interrupt is flaged\n",
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@ -593,7 +593,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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}
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while (status) {
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ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
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ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
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/*
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* Here we must check whether the corresponding GPIO's interrupt
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@ -602,7 +602,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
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pr_debug("%s: gpio id %d idx %d happens\n",
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__func__, bank->id, idx);
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generic_handle_irq(irq_find_mapping(sgpio_chip.chip.gc.irqdomain, idx +
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generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
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bank->id * SIRFSOC_GPIO_BANK_SIZE));
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}
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@ -613,18 +613,20 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
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chained_irq_exit(chip, desc);
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}
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static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
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static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
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unsigned ctrl_offset)
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{
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u32 val;
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val = readl(sgpio_chip.chip.regs + ctrl_offset);
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val = readl(sgpio->chip.regs + ctrl_offset);
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val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
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writel(val, sgpio_chip.chip.regs + ctrl_offset);
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writel(val, sgpio->chip.regs + ctrl_offset);
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}
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static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
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unsigned long flags;
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if (pinctrl_request_gpio(chip->base + offset))
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@ -636,8 +638,8 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
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* default status:
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* set direction as input and mask irq
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*/
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sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
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__sirfsoc_gpio_irq_mask(bank, offset);
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sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
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__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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@ -646,13 +648,14 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
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static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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__sirfsoc_gpio_irq_mask(bank, offset);
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sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
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__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
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sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
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spin_unlock_irqrestore(&bank->lock, flags);
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@ -661,7 +664,8 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
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static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
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int idx = sirfsoc_gpio_to_bankoff(gpio);
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unsigned long flags;
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unsigned offset;
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@ -670,14 +674,16 @@ static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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spin_lock_irqsave(&bank->lock, flags);
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sirfsoc_gpio_set_input(bank, offset);
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sirfsoc_gpio_set_input(sgpio, offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
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static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
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struct sirfsoc_gpio_bank *bank,
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unsigned offset,
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int value)
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{
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u32 out_ctrl;
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@ -685,7 +691,7 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsig
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spin_lock_irqsave(&bank->lock, flags);
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out_ctrl = readl(sgpio_chip.chip.regs + offset);
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out_ctrl = readl(sgpio->chip.regs + offset);
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if (value)
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out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
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else
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@ -693,14 +699,15 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsig
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out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
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writel(out_ctrl, sgpio_chip.chip.regs + offset);
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writel(out_ctrl, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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}
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static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
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int idx = sirfsoc_gpio_to_bankoff(gpio);
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u32 offset;
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unsigned long flags;
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@ -709,7 +716,7 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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spin_lock_irqsave(&sgpio_lock, flags);
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sirfsoc_gpio_set_output(bank, offset, value);
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sirfsoc_gpio_set_output(sgpio, bank, offset, value);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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@ -718,13 +725,14 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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val = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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spin_unlock_irqrestore(&bank->lock, flags);
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@ -734,23 +742,25 @@ static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(offset);
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struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
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struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
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u32 ctrl;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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ctrl = readl(sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
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if (value)
|
||||
ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
|
||||
else
|
||||
ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
|
||||
writel(ctrl, sgpio_chip.chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
|
||||
writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
|
||||
|
||||
spin_unlock_irqrestore(&bank->lock, flags);
|
||||
}
|
||||
|
||||
static void sirfsoc_gpio_set_pullup(const u32 *pullups)
|
||||
static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
|
||||
const u32 *pullups)
|
||||
{
|
||||
int i, n;
|
||||
const unsigned long *p = (const unsigned long *)pullups;
|
||||
|
|
@ -758,15 +768,16 @@ static void sirfsoc_gpio_set_pullup(const u32 *pullups)
|
|||
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
||||
for_each_set_bit(n, p + i, BITS_PER_LONG) {
|
||||
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
|
||||
u32 val = readl(sgpio_chip.chip.regs + offset);
|
||||
u32 val = readl(sgpio->chip.regs + offset);
|
||||
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
|
||||
val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
|
||||
writel(val, sgpio_chip.chip.regs + offset);
|
||||
writel(val, sgpio->chip.regs + offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
|
||||
static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
|
||||
const u32 *pulldowns)
|
||||
{
|
||||
int i, n;
|
||||
const unsigned long *p = (const unsigned long *)pulldowns;
|
||||
|
|
@ -774,10 +785,10 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
|
|||
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
||||
for_each_set_bit(n, p + i, BITS_PER_LONG) {
|
||||
u32 offset = SIRFSOC_GPIO_CTRL(i, n);
|
||||
u32 val = readl(sgpio_chip.chip.regs + offset);
|
||||
u32 val = readl(sgpio->chip.regs + offset);
|
||||
val |= SIRFSOC_GPIO_CTL_PULL_MASK;
|
||||
val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
|
||||
writel(val, sgpio_chip.chip.regs + offset);
|
||||
writel(val, sgpio->chip.regs + offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -785,6 +796,7 @@ static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
|
|||
static int sirfsoc_gpio_probe(struct device_node *np)
|
||||
{
|
||||
int i, err = 0;
|
||||
static struct sirfsoc_gpio_chip *sgpio;
|
||||
struct sirfsoc_gpio_bank *bank;
|
||||
void __iomem *regs;
|
||||
struct platform_device *pdev;
|
||||
|
|
@ -796,6 +808,10 @@ static int sirfsoc_gpio_probe(struct device_node *np)
|
|||
if (!pdev)
|
||||
return -ENODEV;
|
||||
|
||||
sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
|
||||
if (!sgpio)
|
||||
return -ENOMEM;
|
||||
|
||||
regs = of_iomap(np, 0);
|
||||
if (!regs)
|
||||
return -ENOMEM;
|
||||
|
|
@ -803,30 +819,30 @@ static int sirfsoc_gpio_probe(struct device_node *np)
|
|||
if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
|
||||
is_marco = 1;
|
||||
|
||||
sgpio_chip.chip.gc.request = sirfsoc_gpio_request;
|
||||
sgpio_chip.chip.gc.free = sirfsoc_gpio_free;
|
||||
sgpio_chip.chip.gc.direction_input = sirfsoc_gpio_direction_input;
|
||||
sgpio_chip.chip.gc.get = sirfsoc_gpio_get_value;
|
||||
sgpio_chip.chip.gc.direction_output = sirfsoc_gpio_direction_output;
|
||||
sgpio_chip.chip.gc.set = sirfsoc_gpio_set_value;
|
||||
sgpio_chip.chip.gc.base = 0;
|
||||
sgpio_chip.chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
|
||||
sgpio_chip.chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
|
||||
sgpio_chip.chip.gc.of_node = np;
|
||||
sgpio_chip.chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
|
||||
sgpio_chip.chip.gc.of_gpio_n_cells = 2;
|
||||
sgpio_chip.chip.gc.dev = &pdev->dev;
|
||||
sgpio_chip.chip.regs = regs;
|
||||
sgpio_chip.is_marco = is_marco;
|
||||
sgpio->chip.gc.request = sirfsoc_gpio_request;
|
||||
sgpio->chip.gc.free = sirfsoc_gpio_free;
|
||||
sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
|
||||
sgpio->chip.gc.get = sirfsoc_gpio_get_value;
|
||||
sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
|
||||
sgpio->chip.gc.set = sirfsoc_gpio_set_value;
|
||||
sgpio->chip.gc.base = 0;
|
||||
sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
|
||||
sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
|
||||
sgpio->chip.gc.of_node = np;
|
||||
sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
|
||||
sgpio->chip.gc.of_gpio_n_cells = 2;
|
||||
sgpio->chip.gc.dev = &pdev->dev;
|
||||
sgpio->chip.regs = regs;
|
||||
sgpio->is_marco = is_marco;
|
||||
|
||||
err = gpiochip_add(&sgpio_chip.chip.gc);
|
||||
err = gpiochip_add(&sgpio->chip.gc);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
|
||||
np->full_name, err);
|
||||
goto out;
|
||||
}
|
||||
|
||||
err = gpiochip_irqchip_add(&sgpio_chip.chip.gc,
|
||||
err = gpiochip_irqchip_add(&sgpio->chip.gc,
|
||||
&sirfsoc_irq_chip,
|
||||
0, handle_level_irq,
|
||||
IRQ_TYPE_NONE);
|
||||
|
|
@ -837,30 +853,42 @@ static int sirfsoc_gpio_probe(struct device_node *np)
|
|||
}
|
||||
|
||||
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
|
||||
bank = &sgpio_chip.sgpio_bank[i];
|
||||
bank = &sgpio->sgpio_bank[i];
|
||||
spin_lock_init(&bank->lock);
|
||||
bank->parent_irq = platform_get_irq(pdev, i);
|
||||
if (bank->parent_irq < 0) {
|
||||
err = bank->parent_irq;
|
||||
goto out;
|
||||
goto out_banks;
|
||||
}
|
||||
|
||||
gpiochip_set_chained_irqchip(&sgpio_chip.chip.gc,
|
||||
gpiochip_set_chained_irqchip(&sgpio->chip.gc,
|
||||
&sirfsoc_irq_chip,
|
||||
bank->parent_irq,
|
||||
sirfsoc_gpio_handle_irq);
|
||||
}
|
||||
|
||||
err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
|
||||
0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev,
|
||||
"could not add gpiochip pin range\n");
|
||||
goto out_no_range;
|
||||
}
|
||||
|
||||
if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
|
||||
SIRFSOC_GPIO_NO_OF_BANKS))
|
||||
sirfsoc_gpio_set_pullup(pullups);
|
||||
sirfsoc_gpio_set_pullup(sgpio, pullups);
|
||||
|
||||
if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
|
||||
SIRFSOC_GPIO_NO_OF_BANKS))
|
||||
sirfsoc_gpio_set_pulldown(pulldowns);
|
||||
sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
|
||||
|
||||
return 0;
|
||||
|
||||
out_no_range:
|
||||
out_banks:
|
||||
if (gpiochip_remove(&sgpio->chip.gc))
|
||||
dev_err(&pdev->dev, "could not remove gpio chip\n");
|
||||
out:
|
||||
iounmap(regs);
|
||||
return err;
|
||||
|
|
|
|||
Loading…
Reference in a new issue