Merge "drm/msm/sde: Add support for REGDMA broadcast for DSPP"
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2a0c53b3ca
1 changed files with 255 additions and 59 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#include <drm/msm_drm_pp.h>
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#include "sde_reg_dma.h"
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@ -347,6 +347,49 @@ int reg_dmav1_init_dspp_op_v4(int feature, enum sde_dspp idx)
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return rc;
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}
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static int reg_dmav1_get_dspp_blk(struct sde_hw_cp_cfg *hw_cfg,
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enum sde_dspp curr_dspp, u32 *blk)
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{
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struct sde_hw_dspp *dspp;
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int rc = 0;
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if (hw_cfg == NULL) {
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DRM_ERROR("Invalid sde_hw_cp_cfg structure provided\n");
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return -EINVAL;
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}
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if (hw_cfg->dspp == NULL) {
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DRM_ERROR("Invalid sde_hw_dspp structure provided in hw_cfg\n");
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return -EINVAL;
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}
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if (blk == NULL) {
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DRM_ERROR("Invalid payload provided\n");
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return -EINVAL;
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}
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/* Treat first dspp as master to simplify setup */
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dspp = hw_cfg->dspp[0];
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if (curr_dspp != dspp->idx) {
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DRM_DEBUG_DRIVER("Slave DSPP instance %d\n", dspp->idx);
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rc = -EALREADY;
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} else {
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for (u32 i = 0 ; i < hw_cfg->num_of_mixers; i++) {
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dspp = hw_cfg->dspp[i];
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if (dspp->idx >= DSPP_MAX) {
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DRM_ERROR("Invalid dspp idx %d", dspp->idx);
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rc = -EINVAL;
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break;
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}
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*blk |= dspp_mapping[dspp->idx];
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}
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}
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if (!rc && !blk)
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rc = -EINVAL;
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return rc;
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}
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void reg_dmav1_setup_dspp_vlutv18(struct sde_hw_dspp *ctx, void *cfg)
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{
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struct drm_msm_pa_vlut *payload = NULL;
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@ -357,16 +400,31 @@ void reg_dmav1_setup_dspp_vlutv18(struct sde_hw_dspp *ctx, void *cfg)
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struct sde_hw_ctl *ctl = NULL;
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u32 *data = NULL;
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int i, j, rc = 0;
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u32 index, blk = 0;
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rc = reg_dma_dspp_check(ctx, cfg, VLUT);
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if (rc)
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return;
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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ctl = hw_cfg->ctl;
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if (!hw_cfg->payload) {
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struct sde_hw_dspp *dspp;
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DRM_DEBUG_DRIVER("Disable vlut feature\n");
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SDE_REG_WRITE(&ctx->hw,
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ctx->cap->sblk->hist.base + PA_LUTV_DSPP_CTRL_OFF, 0);
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for (index = 0; index < hw_cfg->num_of_mixers; index++) {
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dspp = hw_cfg->dspp[index];
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SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->hist.base +
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PA_LUTV_DSPP_CTRL_OFF, 0);
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}
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goto exit;
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}
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@ -379,8 +437,7 @@ void reg_dmav1_setup_dspp_vlutv18(struct sde_hw_dspp *ctx, void *cfg)
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[VLUT][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
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VLUT, dspp_buf[VLUT][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, VLUT, dspp_buf[VLUT][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -438,8 +495,15 @@ void reg_dmav1_setup_dspp_vlutv18(struct sde_hw_dspp *ctx, void *cfg)
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exit:
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kfree(data);
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/* update flush bit */
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if (!rc && ctl && ctl->ops.update_bitmask_dspp_pavlut)
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ctl->ops.update_bitmask_dspp_pavlut(ctl, ctx->idx, true);
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if (!rc && ctl && ctl->ops.update_bitmask_dspp_pavlut) {
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int dspp_idx;
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for (index = 0; index < hw_cfg->num_of_mixers; index++) {
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dspp_idx = hw_cfg->dspp[index]->idx;
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ctl->ops.update_bitmask_dspp_pavlut(ctl, dspp_idx,
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true);
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}
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}
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}
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static int sde_gamut_get_mode_info(u32 pipe, struct drm_msm_3d_gamut *payload,
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@ -509,12 +573,20 @@ static void dspp_3d_gamutv4_off(struct sde_hw_dspp *ctx, void *cfg)
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struct sde_hw_reg_dma_ops *dma_ops;
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struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
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int rc;
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u32 blk = 0;
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[GAMUT][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], GAMUT,
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dspp_buf[GAMUT][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, GAMUT, dspp_buf[GAMUT][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -551,6 +623,7 @@ static void reg_dmav1_setup_dspp_3d_gamutv4_common(struct sde_hw_dspp *ctx,
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struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
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struct sde_hw_reg_dma_ops *dma_ops;
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int rc;
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u32 blk = 0;
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rc = reg_dma_dspp_check(ctx, cfg, GAMUT);
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if (rc)
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@ -576,11 +649,18 @@ static void reg_dmav1_setup_dspp_3d_gamutv4_common(struct sde_hw_dspp *ctx,
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return;
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}
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[GAMUT][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], GAMUT,
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dspp_buf[GAMUT][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, GAMUT, dspp_buf[GAMUT][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -669,6 +749,7 @@ void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg)
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struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
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int rc, i = 0;
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u32 reg;
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u32 blk = 0;
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rc = reg_dma_dspp_check(ctx, cfg, GC);
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if (rc)
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@ -685,13 +766,21 @@ void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg)
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hw_cfg->len, sizeof(struct drm_msm_pgc_lut));
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return;
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}
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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lut_cfg = hw_cfg->payload;
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[GC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], GC,
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dspp_buf[GC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, GC, dspp_buf[GC][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -762,12 +851,20 @@ static void _dspp_igcv31_off(struct sde_hw_dspp *ctx, void *cfg)
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struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
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int rc;
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u32 reg;
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u32 blk = 0;
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[IGC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], IGC,
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dspp_buf[IGC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, IGC, dspp_buf[IGC][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -804,6 +901,7 @@ void reg_dmav1_setup_dspp_igcv31(struct sde_hw_dspp *ctx, void *cfg)
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u32 *addr = NULL;
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u32 offset = 0;
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u32 reg;
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u32 index, dspp_sel, blk = 0;
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rc = reg_dma_dspp_check(ctx, cfg, IGC);
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if (rc)
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@ -821,6 +919,14 @@ void reg_dmav1_setup_dspp_igcv31(struct sde_hw_dspp *ctx, void *cfg)
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return;
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}
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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lut_cfg = hw_cfg->payload;
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dma_ops = sde_reg_dma_get_ops();
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@ -835,13 +941,17 @@ void reg_dmav1_setup_dspp_igcv31(struct sde_hw_dspp *ctx, void *cfg)
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return;
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}
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dspp_sel = -1;
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for (index = 0; index < hw_cfg->num_of_mixers; index++)
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dspp_sel &= IGC_DSPP_SEL_MASK(hw_cfg->dspp[index]->idx - 1);
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for (i = 0; i < IGC_TBL_NUM; i++) {
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addr = lut_cfg->c0 + (i * ARRAY_SIZE(lut_cfg->c0));
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offset = IGC_C0_OFF + (i * sizeof(u32));
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for (j = 0; j < IGC_TBL_LEN; j++) {
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addr[j] &= IGC_DATA_MASK;
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addr[j] |= IGC_DSPP_SEL_MASK(ctx->idx - 1);
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addr[j] |= dspp_sel;
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if (j == 0)
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addr[j] |= IGC_INDEX_UPDATE;
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}
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@ -856,8 +966,7 @@ void reg_dmav1_setup_dspp_igcv31(struct sde_hw_dspp *ctx, void *cfg)
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}
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}
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], IGC,
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dspp_buf[IGC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, IGC, dspp_buf[IGC][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -903,12 +1012,20 @@ static void _dspp_pccv4_off(struct sde_hw_dspp *ctx, void *cfg)
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struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
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int rc;
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u32 reg;
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u32 blk = 0;
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[PCC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx], PCC,
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dspp_buf[PCC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, PCC, dspp_buf[PCC][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -945,6 +1062,7 @@ void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
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u32 *data = NULL;
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int rc, i = 0;
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u32 reg = 0;
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u32 blk = 0;
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rc = reg_dma_dspp_check(ctx, cfg, PCC);
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if (rc)
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@ -962,13 +1080,20 @@ void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
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return;
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}
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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pcc_cfg = hw_cfg->payload;
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[PCC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
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PCC, dspp_buf[PCC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, PCC, dspp_buf[PCC][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -1055,6 +1180,7 @@ void reg_dmav1_setup_dspp_pa_hsicv17(struct sde_hw_dspp *ctx, void *cfg)
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struct drm_msm_pa_hsic *hsic_cfg;
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u32 reg = 0, opcode = 0, local_opcode = 0;
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int rc;
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u32 blk = 0;
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opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
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@ -1077,13 +1203,20 @@ void reg_dmav1_setup_dspp_pa_hsicv17(struct sde_hw_dspp *ctx, void *cfg)
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return;
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}
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rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
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if (rc == -EINVAL) {
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DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
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return;
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} else if (rc == -EALREADY) {
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return;
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}
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hsic_cfg = hw_cfg->payload;
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dma_ops = sde_reg_dma_get_ops();
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dma_ops->reset_reg_dma_buf(dspp_buf[HSIC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
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HSIC, dspp_buf[HSIC][ctx->idx]);
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REG_DMA_INIT_OPS(dma_write_cfg, blk, HSIC, dspp_buf[HSIC][ctx->idx]);
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REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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@ -1151,13 +1284,28 @@ void reg_dmav1_setup_dspp_pa_hsicv17(struct sde_hw_dspp *ctx, void *cfg)
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return;
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}
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REG_DMA_SETUP_OPS(dma_write_cfg,
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ctx->cap->sblk->hsic.base, &local_opcode, sizeof(local_opcode),
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REG_SINGLE_MODIFY, 0, 0, REG_DMA_PA_MODE_HSIC_MASK);
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rc = dma_ops->setup_payload(&dma_write_cfg);
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if (rc) {
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DRM_ERROR("setting opcode failed ret %d\n", rc);
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return;
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for (int i = 0; i < hw_cfg->num_of_mixers; i++) {
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blk = dspp_mapping[hw_cfg->dspp[i]->idx];
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REG_DMA_INIT_OPS(dma_write_cfg, blk, HSIC,
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dspp_buf[HSIC][ctx->idx]);
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|
||||
REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT,
|
||||
0, 0, 0);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("write decode select failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg,
|
||||
ctx->cap->sblk->hsic.base, &local_opcode,
|
||||
sizeof(local_opcode), REG_SINGLE_MODIFY, 0, 0,
|
||||
REG_DMA_PA_MODE_HSIC_MASK);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("setting opcode failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[HSIC][ctx->idx],
|
||||
|
|
@ -1176,6 +1324,7 @@ void reg_dmav1_setup_dspp_sixzonev17(struct sde_hw_dspp *ctx, void *cfg)
|
|||
struct drm_msm_sixzone *sixzone;
|
||||
u32 reg = 0, local_hold = 0;
|
||||
u32 opcode = 0, local_opcode = 0;
|
||||
u32 blk = 0;
|
||||
int rc;
|
||||
|
||||
opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
|
||||
|
|
@ -1200,13 +1349,21 @@ void reg_dmav1_setup_dspp_sixzonev17(struct sde_hw_dspp *ctx, void *cfg)
|
|||
return;
|
||||
}
|
||||
|
||||
rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
|
||||
if (rc == -EINVAL) {
|
||||
DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
|
||||
return;
|
||||
} else if (rc == -EALREADY) {
|
||||
return;
|
||||
}
|
||||
|
||||
sixzone = hw_cfg->payload;
|
||||
|
||||
dma_ops = sde_reg_dma_get_ops();
|
||||
dma_ops->reset_reg_dma_buf(dspp_buf[SIX_ZONE][ctx->idx]);
|
||||
|
||||
REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
|
||||
SIX_ZONE, dspp_buf[SIX_ZONE][ctx->idx]);
|
||||
REG_DMA_INIT_OPS(dma_write_cfg, blk, SIX_ZONE,
|
||||
dspp_buf[SIX_ZONE][ctx->idx]);
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
|
|
@ -1270,15 +1427,30 @@ void reg_dmav1_setup_dspp_sixzonev17(struct sde_hw_dspp *ctx, void *cfg)
|
|||
DRM_ERROR("Invalid six zone config 0x%x\n", local_opcode);
|
||||
return;
|
||||
}
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg,
|
||||
ctx->cap->sblk->hsic.base, &local_opcode, sizeof(local_opcode),
|
||||
REG_SINGLE_MODIFY, 0, 0, REG_DMA_PA_MODE_SZONE_MASK);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("setting local_opcode failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
|
||||
for (int i = 0; i < hw_cfg->num_of_mixers; i++) {
|
||||
blk = dspp_mapping[hw_cfg->dspp[i]->idx];
|
||||
REG_DMA_INIT_OPS(dma_write_cfg, blk, SIX_ZONE,
|
||||
dspp_buf[SIX_ZONE][ctx->idx]);
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT,
|
||||
0, 0, 0);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("write decode select failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg,
|
||||
ctx->cap->sblk->hsic.base, &local_opcode,
|
||||
sizeof(local_opcode), REG_SINGLE_MODIFY, 0, 0,
|
||||
REG_DMA_PA_MODE_SZONE_MASK);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("setting local_opcode failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
}
|
||||
REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
|
||||
dspp_buf[SIX_ZONE][ctx->idx],
|
||||
REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
|
||||
|
|
@ -1322,6 +1494,7 @@ static void __setup_dspp_memcol(struct sde_hw_dspp *ctx,
|
|||
u32 addr = 0, idx = 0;
|
||||
u32 hold = 0, hold_shift = 0, mask = 0xFFFF;
|
||||
u32 opcode = 0, opcode_mask = 0xFFFFFFFF;
|
||||
u32 blk = 0;
|
||||
|
||||
switch (type) {
|
||||
case MEMC_SKIN:
|
||||
|
|
@ -1341,11 +1514,18 @@ static void __setup_dspp_memcol(struct sde_hw_dspp *ctx,
|
|||
return;
|
||||
}
|
||||
|
||||
rc = reg_dmav1_get_dspp_blk(hw_cfg, ctx->idx, &blk);
|
||||
if (rc == -EINVAL) {
|
||||
DRM_ERROR("unable to determine LUTDMA DSPP blocks\n");
|
||||
return;
|
||||
} else if (rc == -EALREADY) {
|
||||
return;
|
||||
}
|
||||
|
||||
dma_ops = sde_reg_dma_get_ops();
|
||||
dma_ops->reset_reg_dma_buf(dspp_buf[type][ctx->idx]);
|
||||
|
||||
REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
|
||||
type, dspp_buf[type][ctx->idx]);
|
||||
REG_DMA_INIT_OPS(dma_write_cfg, blk, type, dspp_buf[type][ctx->idx]);
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
|
|
@ -1392,24 +1572,40 @@ static void __setup_dspp_memcol(struct sde_hw_dspp *ctx,
|
|||
hold = ((memcolor->sat_hold & REG_MASK(2)) << hold_shift);
|
||||
hold |= ((memcolor->val_hold & REG_MASK(2)) << (hold_shift + 2));
|
||||
mask &= ~REG_MASK_SHIFT(4, hold_shift);
|
||||
/* write sat_hold and val_hold in PA_PWL_HOLD */
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg, addr, &hold, sizeof(hold),
|
||||
REG_SINGLE_MODIFY, 0, 0, mask);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("setting color_adjust_p0 failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
|
||||
opcode |= PA_EN;
|
||||
opcode_mask &= ~(opcode);
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg,
|
||||
ctx->cap->sblk->hsic.base, &opcode, sizeof(opcode),
|
||||
REG_SINGLE_MODIFY, 0, 0, opcode_mask);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("setting opcode failed ret %d\n", rc);
|
||||
return;
|
||||
|
||||
/* write sat_hold and val_hold in PA_PWL_HOLD */
|
||||
for (int i = 0; i < hw_cfg->num_of_mixers; i++) {
|
||||
blk = dspp_mapping[hw_cfg->dspp[i]->idx];
|
||||
REG_DMA_INIT_OPS(dma_write_cfg, blk, type,
|
||||
dspp_buf[type][ctx->idx]);
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT,
|
||||
0, 0, 0);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("write decode select failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg, addr, &hold, sizeof(hold),
|
||||
REG_SINGLE_MODIFY, 0, 0, mask);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("setting color_adjust_p0 failed ret %d\n",
|
||||
rc);
|
||||
return;
|
||||
}
|
||||
|
||||
REG_DMA_SETUP_OPS(dma_write_cfg,
|
||||
ctx->cap->sblk->hsic.base, &opcode, sizeof(opcode),
|
||||
REG_SINGLE_MODIFY, 0, 0, opcode_mask);
|
||||
rc = dma_ops->setup_payload(&dma_write_cfg);
|
||||
if (rc) {
|
||||
DRM_ERROR("setting opcode failed ret %d\n", rc);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
|
||||
|
|
|
|||
Loading…
Reference in a new issue