ath9k_hw: add definitions to support MCI h/w code
these definitions will be used by MCI state machine and the corresponding hardware code Cc: Wilson Tsao <wtsao@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Mohammed Shafi Shajakhan
John W. Linville
parent
24bf330485
commit
2ee4bd1e25
4 changed files with 529 additions and 26 deletions
102
drivers/net/wireless/ath/ath9k/ar9003_mci.h
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102
drivers/net/wireless/ath/ath9k/ar9003_mci.h
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@ -0,0 +1,102 @@
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/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef AR9003_MCI_H
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#define AR9003_MCI_H
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#define MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
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/* Default remote BT device MCI COEX version */
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#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
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#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
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/* Local WLAN MCI COEX version */
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#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
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#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
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enum mci_gpm_coex_query_type {
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MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0),
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MCI_GPM_COEX_QUERY_BT_TOPOLOGY = BIT(1),
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MCI_GPM_COEX_QUERY_BT_DEBUG = BIT(2),
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};
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enum mci_gpm_coex_halt_bt_gpm {
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MCI_GPM_COEX_BT_GPM_UNHALT,
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MCI_GPM_COEX_BT_GPM_HALT
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};
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enum mci_gpm_coex_bt_update_flags_op {
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MCI_GPM_COEX_BT_FLAGS_READ,
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MCI_GPM_COEX_BT_FLAGS_SET,
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MCI_GPM_COEX_BT_FLAGS_CLEAR
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};
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#define MCI_NUM_BT_CHANNELS 79
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#define MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
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#define MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
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#define MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
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#define MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
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#define MCI_BT_MCI_FLAGS_DEBUG 0x00000020
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#define MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
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#define MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
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#define MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
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#define MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
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#define MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
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#define MCI_BT_MCI_FLAGS_AR9462_MODE 0x00001000
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#define MCI_BT_MCI_FLAGS_OTHER 0x00010000
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#define MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
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#define MCI_TOGGLE_BT_MCI_FLAGS (MCI_BT_MCI_FLAGS_UPDATE_CORR | \
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MCI_BT_MCI_FLAGS_UPDATE_HDR | \
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MCI_BT_MCI_FLAGS_UPDATE_PLD | \
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MCI_BT_MCI_FLAGS_MCI_MODE)
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#define MCI_2G_FLAGS_CLEAR_MASK 0x00000000
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#define MCI_2G_FLAGS_SET_MASK MCI_TOGGLE_BT_MCI_FLAGS
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#define MCI_2G_FLAGS MCI_DEFAULT_BT_MCI_FLAGS
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#define MCI_5G_FLAGS_CLEAR_MASK MCI_TOGGLE_BT_MCI_FLAGS
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#define MCI_5G_FLAGS_SET_MASK 0x00000000
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#define MCI_5G_FLAGS (MCI_DEFAULT_BT_MCI_FLAGS & \
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~MCI_TOGGLE_BT_MCI_FLAGS)
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/*
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* Default value for AR9462 is 0x00002201
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*/
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#define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
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#define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
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#define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
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#define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
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#define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
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#define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
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#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
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#define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
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#define ATH_MCI_CONFIG_AGGR_THRESH_S 8
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#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
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#define ATH_MCI_CONFIG_CLK_DIV 0x00003000
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#define ATH_MCI_CONFIG_CLK_DIV_S 12
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#define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
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#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
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#define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
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#define ATH_MCI_CONFIG_MCI_OBS_MASK (ATH_MCI_CONFIG_MCI_OBS_MCI | \
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ATH_MCI_CONFIG_MCI_OBS_TXRX | \
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ATH_MCI_CONFIG_MCI_OBS_BT)
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#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
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#endif
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@ -490,6 +490,8 @@
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#define AR_PHY_TEST_CTL_TSTADC_EN_S 8
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#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
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#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
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#define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000
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#define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29
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#define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)
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@ -1001,6 +1003,7 @@
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/* GLB Registers */
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#define AR_GLB_BASE 0x20000
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#define AR_GLB_GPIO_CONTROL (AR_GLB_BASE)
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#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
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#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \
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(AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
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@ -266,6 +266,7 @@ enum ath9k_int {
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ATH9K_INT_TX = 0x00000040,
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ATH9K_INT_TXDESC = 0x00000080,
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ATH9K_INT_TIM_TIMER = 0x00000100,
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ATH9K_INT_MCI = 0x00000200,
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ATH9K_INT_BB_WATCHDOG = 0x00000400,
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ATH9K_INT_TXURN = 0x00000800,
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ATH9K_INT_MIB = 0x00001000,
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@ -417,6 +418,25 @@ enum ath9k_rx_qtype {
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ATH9K_RX_QUEUE_MAX,
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};
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enum mci_message_header { /* length of payload */
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MCI_LNA_CTRL = 0x10, /* len = 0 */
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MCI_CONT_NACK = 0x20, /* len = 0 */
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MCI_CONT_INFO = 0x30, /* len = 4 */
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MCI_CONT_RST = 0x40, /* len = 0 */
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MCI_SCHD_INFO = 0x50, /* len = 16 */
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MCI_CPU_INT = 0x60, /* len = 4 */
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MCI_SYS_WAKING = 0x70, /* len = 0 */
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MCI_GPM = 0x80, /* len = 16 */
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MCI_LNA_INFO = 0x90, /* len = 1 */
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MCI_LNA_STATE = 0x94,
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MCI_LNA_TAKE = 0x98,
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MCI_LNA_TRANS = 0x9c,
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MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
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MCI_REQ_WAKE = 0xc0, /* len = 0 */
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MCI_DEBUG_16 = 0xfe, /* len = 2 */
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MCI_REMOTE_RESET = 0xff /* len = 16 */
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};
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enum ath_mci_gpm_coex_profile_type {
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MCI_GPM_COEX_PROFILE_UNKNOWN,
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MCI_GPM_COEX_PROFILE_RFCOMM,
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@ -427,6 +447,132 @@ enum ath_mci_gpm_coex_profile_type {
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MCI_GPM_COEX_PROFILE_MAX
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};
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/* MCI GPM/Coex opcode/type definitions */
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enum {
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MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
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MCI_GPM_COEX_B_GPM_TYPE = 4,
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MCI_GPM_COEX_B_GPM_OPCODE = 5,
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/* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
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MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
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/* MCI_GPM_COEX_VERSION_QUERY */
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/* MCI_GPM_COEX_VERSION_RESPONSE */
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MCI_GPM_COEX_B_MAJOR_VERSION = 6,
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MCI_GPM_COEX_B_MINOR_VERSION = 7,
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/* MCI_GPM_COEX_STATUS_QUERY */
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MCI_GPM_COEX_B_BT_BITMAP = 6,
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MCI_GPM_COEX_B_WLAN_BITMAP = 7,
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/* MCI_GPM_COEX_HALT_BT_GPM */
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MCI_GPM_COEX_B_HALT_STATE = 6,
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/* MCI_GPM_COEX_WLAN_CHANNELS */
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MCI_GPM_COEX_B_CHANNEL_MAP = 6,
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/* MCI_GPM_COEX_BT_PROFILE_INFO */
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MCI_GPM_COEX_B_PROFILE_TYPE = 6,
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MCI_GPM_COEX_B_PROFILE_LINKID = 7,
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MCI_GPM_COEX_B_PROFILE_STATE = 8,
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MCI_GPM_COEX_B_PROFILE_ROLE = 9,
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MCI_GPM_COEX_B_PROFILE_RATE = 10,
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MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
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MCI_GPM_COEX_H_PROFILE_T = 12,
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MCI_GPM_COEX_B_PROFILE_W = 14,
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MCI_GPM_COEX_B_PROFILE_A = 15,
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/* MCI_GPM_COEX_BT_STATUS_UPDATE */
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MCI_GPM_COEX_B_STATUS_TYPE = 6,
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MCI_GPM_COEX_B_STATUS_LINKID = 7,
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MCI_GPM_COEX_B_STATUS_STATE = 8,
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/* MCI_GPM_COEX_BT_UPDATE_FLAGS */
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MCI_GPM_COEX_W_BT_FLAGS = 6,
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MCI_GPM_COEX_B_BT_FLAGS_OP = 10
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};
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enum mci_gpm_subtype {
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MCI_GPM_BT_CAL_REQ = 0,
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MCI_GPM_BT_CAL_GRANT = 1,
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MCI_GPM_BT_CAL_DONE = 2,
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MCI_GPM_WLAN_CAL_REQ = 3,
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MCI_GPM_WLAN_CAL_GRANT = 4,
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MCI_GPM_WLAN_CAL_DONE = 5,
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MCI_GPM_COEX_AGENT = 0x0c,
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MCI_GPM_RSVD_PATTERN = 0xfe,
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MCI_GPM_RSVD_PATTERN32 = 0xfefefefe,
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MCI_GPM_BT_DEBUG = 0xff
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};
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enum mci_bt_state {
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MCI_BT_SLEEP,
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MCI_BT_AWAKE,
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MCI_BT_CAL_START,
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MCI_BT_CAL
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};
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/* Type of state query */
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enum mci_state_type {
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MCI_STATE_ENABLE,
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MCI_STATE_INIT_GPM_OFFSET,
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MCI_STATE_NEXT_GPM_OFFSET,
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MCI_STATE_LAST_GPM_OFFSET,
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MCI_STATE_BT,
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MCI_STATE_SET_BT_SLEEP,
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MCI_STATE_SET_BT_AWAKE,
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MCI_STATE_SET_BT_CAL_START,
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MCI_STATE_SET_BT_CAL,
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MCI_STATE_LAST_SCHD_MSG_OFFSET,
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MCI_STATE_REMOTE_SLEEP,
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MCI_STATE_CONT_RSSI_POWER,
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MCI_STATE_CONT_PRIORITY,
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MCI_STATE_CONT_TXRX,
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MCI_STATE_RESET_REQ_WAKE,
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MCI_STATE_SEND_WLAN_COEX_VERSION,
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MCI_STATE_SET_BT_COEX_VERSION,
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MCI_STATE_SEND_WLAN_CHANNELS,
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MCI_STATE_SEND_VERSION_QUERY,
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MCI_STATE_SEND_STATUS_QUERY,
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MCI_STATE_NEED_FLUSH_BT_INFO,
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MCI_STATE_SET_CONCUR_TX_PRI,
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MCI_STATE_RECOVER_RX,
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MCI_STATE_NEED_FTP_STOMP,
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MCI_STATE_NEED_TUNING,
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MCI_STATE_DEBUG,
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MCI_STATE_MAX
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};
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enum mci_gpm_coex_opcode {
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MCI_GPM_COEX_VERSION_QUERY,
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MCI_GPM_COEX_VERSION_RESPONSE,
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MCI_GPM_COEX_STATUS_QUERY,
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MCI_GPM_COEX_HALT_BT_GPM,
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MCI_GPM_COEX_WLAN_CHANNELS,
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MCI_GPM_COEX_BT_PROFILE_INFO,
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MCI_GPM_COEX_BT_STATUS_UPDATE,
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MCI_GPM_COEX_BT_UPDATE_FLAGS
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};
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#define MCI_GPM_NOMORE 0
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#define MCI_GPM_MORE 1
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#define MCI_GPM_INVALID 0xffffffff
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#define MCI_GPM_RECYCLE(_p_gpm) do { \
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*(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \
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MCI_GPM_RSVD_PATTERN32; \
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} while (0)
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#define MCI_GPM_TYPE(_p_gpm) \
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(*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
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#define MCI_GPM_OPCODE(_p_gpm) \
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(*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
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#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do { \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\
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} while (0)
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#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do { \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\
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} while (0)
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#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
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struct ath9k_beacon_state {
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u32 bs_nexttbtt;
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u32 bs_nextdtim;
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@ -1006,6 +1006,8 @@ enum {
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#define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
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#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000
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#define AR_INTR_ASYNC_MASK_GPIO_S 18
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#define AR_INTR_ASYNC_MASK_MCI 0x00000080
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#define AR_INTR_ASYNC_MASK_MCI_S 7
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#define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034)
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#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
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@ -1013,6 +1015,14 @@ enum {
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#define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
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#define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
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#define AR_INTR_ASYNC_CAUSE_MCI 0x00000080
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#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | \
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AR_INTR_ASYNC_CAUSE_MCI)
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/* Asynchronous Interrupt Enable Register */
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#define AR_INTR_ASYNC_ENABLE_MCI 0x00000080
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#define AR_INTR_ASYNC_ENABLE_MCI_S 7
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#define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
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#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000
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@ -1555,6 +1565,8 @@ enum {
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#define AR_DIAG_FRAME_NV0 0x00020000
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#define AR_DIAG_OBS_PT_SEL1 0x000C0000
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#define AR_DIAG_OBS_PT_SEL1_S 18
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#define AR_DIAG_OBS_PT_SEL2 0x08000000
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#define AR_DIAG_OBS_PT_SEL2_S 27
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#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */
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#define AR_DIAG_IGNORE_VIRT_CS 0x00200000
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#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000
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@ -1929,37 +1941,277 @@ enum {
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#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
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/* MCI Registers */
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#define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c
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#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
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#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0
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#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
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#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
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#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4
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#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
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#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5
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#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
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#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6
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#define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12
|
||||
#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \
|
||||
|
||||
#define AR_MCI_COMMAND0 0x1800
|
||||
#define AR_MCI_COMMAND0_HEADER 0xFF
|
||||
#define AR_MCI_COMMAND0_HEADER_S 0
|
||||
#define AR_MCI_COMMAND0_LEN 0x1f00
|
||||
#define AR_MCI_COMMAND0_LEN_S 8
|
||||
#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000
|
||||
#define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13
|
||||
|
||||
#define AR_MCI_COMMAND1 0x1804
|
||||
|
||||
#define AR_MCI_COMMAND2 0x1808
|
||||
#define AR_MCI_COMMAND2_RESET_TX 0x01
|
||||
#define AR_MCI_COMMAND2_RESET_TX_S 0
|
||||
#define AR_MCI_COMMAND2_RESET_RX 0x02
|
||||
#define AR_MCI_COMMAND2_RESET_RX_S 1
|
||||
#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC
|
||||
#define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2
|
||||
#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400
|
||||
#define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10
|
||||
|
||||
#define AR_MCI_RX_CTRL 0x180c
|
||||
|
||||
#define AR_MCI_TX_CTRL 0x1810
|
||||
/* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */
|
||||
#define AR_MCI_TX_CTRL_CLK_DIV 0x03
|
||||
#define AR_MCI_TX_CTRL_CLK_DIV_S 0
|
||||
#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04
|
||||
#define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2
|
||||
#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8
|
||||
#define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3
|
||||
#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000
|
||||
#define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24
|
||||
|
||||
#define AR_MCI_MSG_ATTRIBUTES_TABLE 0x1814
|
||||
#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF
|
||||
#define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0
|
||||
#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000
|
||||
#define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16
|
||||
|
||||
#define AR_MCI_SCHD_TABLE_0 0x1818
|
||||
#define AR_MCI_SCHD_TABLE_1 0x181c
|
||||
#define AR_MCI_GPM_0 0x1820
|
||||
#define AR_MCI_GPM_1 0x1824
|
||||
#define AR_MCI_GPM_WRITE_PTR 0xFFFF0000
|
||||
#define AR_MCI_GPM_WRITE_PTR_S 16
|
||||
#define AR_MCI_GPM_BUF_LEN 0x0000FFFF
|
||||
#define AR_MCI_GPM_BUF_LEN_S 0
|
||||
|
||||
#define AR_MCI_INTERRUPT_RAW 0x1828
|
||||
#define AR_MCI_INTERRUPT_EN 0x182c
|
||||
#define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
|
||||
#define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0
|
||||
#define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
|
||||
#define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1
|
||||
#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004
|
||||
#define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2
|
||||
#define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
|
||||
#define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3
|
||||
#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
|
||||
#define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4
|
||||
#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
|
||||
#define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5
|
||||
#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
|
||||
#define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7
|
||||
#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
|
||||
#define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8
|
||||
#define AR_MCI_INTERRUPT_RX_MSG 0x00000200
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_S 9
|
||||
#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
|
||||
#define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10
|
||||
#define AR_MCI_INTERRUPT_BT_PRI 0x07fff800
|
||||
#define AR_MCI_INTERRUPT_BT_PRI_S 11
|
||||
#define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000
|
||||
#define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27
|
||||
#define AR_MCI_INTERRUPT_BT_FREQ 0x10000000
|
||||
#define AR_MCI_INTERRUPT_BT_FREQ_S 28
|
||||
#define AR_MCI_INTERRUPT_BT_STOMP 0x20000000
|
||||
#define AR_MCI_INTERRUPT_BT_STOMP_S 29
|
||||
#define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000
|
||||
#define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30
|
||||
#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
|
||||
#define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31
|
||||
|
||||
#define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \
|
||||
AR_MCI_INTERRUPT_RX_INVALID_HDR | \
|
||||
AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
|
||||
AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
|
||||
AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
|
||||
AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \
|
||||
AR_MCI_INTERRUPT_RX_MSG | \
|
||||
AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \
|
||||
AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)
|
||||
|
||||
#define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
|
||||
AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
|
||||
AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
|
||||
AR_MCI_INTERRUPT_TX_SW_MSG_FAIL)
|
||||
|
||||
#define AR_MCI_REMOTE_CPU_INT 0x1830
|
||||
#define AR_MCI_REMOTE_CPU_INT_EN 0x1834
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12
|
||||
#define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \
|
||||
AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
|
||||
|
||||
#define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \
|
||||
AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \
|
||||
AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_CONT_RST | \
|
||||
AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
|
||||
|
||||
#define AR_MCI_CPU_INT 0x1840
|
||||
|
||||
#define AR_MCI_RX_STATUS 0x1844
|
||||
#define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00
|
||||
#define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8
|
||||
#define AR_MCI_RX_REMOTE_SLEEP 0x00001000
|
||||
#define AR_MCI_RX_REMOTE_SLEEP_S 12
|
||||
#define AR_MCI_RX_MCI_CLK_REQ 0x00002000
|
||||
#define AR_MCI_RX_MCI_CLK_REQ_S 13
|
||||
|
||||
#define AR_MCI_CONT_STATUS 0x1848
|
||||
#define AR_MCI_CONT_RSSI_POWER 0x000000FF
|
||||
#define AR_MCI_CONT_RSSI_POWER_S 0
|
||||
#define AR_MCI_CONT_RRIORITY 0x0000FF00
|
||||
#define AR_MCI_CONT_RRIORITY_S 8
|
||||
#define AR_MCI_CONT_TXRX 0x00010000
|
||||
#define AR_MCI_CONT_TXRX_S 16
|
||||
|
||||
#define AR_MCI_BT_PRI0 0x184c
|
||||
#define AR_MCI_BT_PRI1 0x1850
|
||||
#define AR_MCI_BT_PRI2 0x1854
|
||||
#define AR_MCI_BT_PRI3 0x1858
|
||||
#define AR_MCI_BT_PRI 0x185c
|
||||
#define AR_MCI_WL_FREQ0 0x1860
|
||||
#define AR_MCI_WL_FREQ1 0x1864
|
||||
#define AR_MCI_WL_FREQ2 0x1868
|
||||
#define AR_MCI_GAIN 0x186c
|
||||
#define AR_MCI_WBTIMER1 0x1870
|
||||
#define AR_MCI_WBTIMER2 0x1874
|
||||
#define AR_MCI_WBTIMER3 0x1878
|
||||
#define AR_MCI_WBTIMER4 0x187c
|
||||
#define AR_MCI_MAXGAIN 0x1880
|
||||
#define AR_MCI_HW_SCHD_TBL_CTL 0x1884
|
||||
#define AR_MCI_HW_SCHD_TBL_D0 0x1888
|
||||
#define AR_MCI_HW_SCHD_TBL_D1 0x188c
|
||||
#define AR_MCI_HW_SCHD_TBL_D2 0x1890
|
||||
#define AR_MCI_HW_SCHD_TBL_D3 0x1894
|
||||
#define AR_MCI_TX_PAYLOAD0 0x1898
|
||||
#define AR_MCI_TX_PAYLOAD1 0x189c
|
||||
#define AR_MCI_TX_PAYLOAD2 0x18a0
|
||||
#define AR_MCI_TX_PAYLOAD3 0x18a4
|
||||
#define AR_BTCOEX_WBTIMER 0x18a8
|
||||
|
||||
#define AR_BTCOEX_CTRL 0x18ac
|
||||
#define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001
|
||||
#define AR_BTCOEX_CTRL_AR9462_MODE_S 0
|
||||
#define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002
|
||||
#define AR_BTCOEX_CTRL_WBTIMER_EN_S 1
|
||||
#define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004
|
||||
#define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2
|
||||
#define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008
|
||||
#define AR_BTCOEX_CTRL_LNA_SHARED_S 3
|
||||
#define AR_BTCOEX_CTRL_PA_SHARED 0x00000010
|
||||
#define AR_BTCOEX_CTRL_PA_SHARED_S 4
|
||||
#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020
|
||||
#define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5
|
||||
#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040
|
||||
#define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6
|
||||
#define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180
|
||||
#define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7
|
||||
#define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00
|
||||
#define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9
|
||||
#define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000
|
||||
#define AR_BTCOEX_CTRL_AGGR_THRESH_S 12
|
||||
#define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000
|
||||
#define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19
|
||||
#define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000
|
||||
#define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20
|
||||
#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000
|
||||
#define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28
|
||||
#define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000
|
||||
#define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29
|
||||
#define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000
|
||||
#define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30
|
||||
#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000
|
||||
#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31
|
||||
|
||||
#define AR_BTCOEX_WL_WEIGHTS0 0x18b0
|
||||
#define AR_BTCOEX_WL_WEIGHTS1 0x18b4
|
||||
#define AR_BTCOEX_WL_WEIGHTS2 0x18b8
|
||||
#define AR_BTCOEX_WL_WEIGHTS3 0x18bc
|
||||
#define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2))
|
||||
#define AR_BTCOEX_WL_LNA 0x1940
|
||||
#define AR_BTCOEX_RFGAIN_CTRL 0x1944
|
||||
|
||||
#define AR_BTCOEX_CTRL2 0x1948
|
||||
#define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800
|
||||
#define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11
|
||||
#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000
|
||||
#define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19
|
||||
#define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000
|
||||
#define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22
|
||||
#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000
|
||||
#define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23
|
||||
#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000
|
||||
#define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24
|
||||
#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000
|
||||
#define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25
|
||||
|
||||
#define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001
|
||||
#define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0
|
||||
#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002
|
||||
#define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1
|
||||
#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004
|
||||
#define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2
|
||||
#define AR_GLB_WLAN_UART_INTF_EN 0x00020000
|
||||
#define AR_GLB_WLAN_UART_INTF_EN_S 17
|
||||
#define AR_GLB_DS_JTAG_DISABLE 0x00040000
|
||||
#define AR_GLB_DS_JTAG_DISABLE_S 18
|
||||
|
||||
#define AR_BTCOEX_RC 0x194c
|
||||
#define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2))
|
||||
#define AR_BTCOEX_DBG 0x1a50
|
||||
#define AR_MCI_LAST_HW_MSG_HDR 0x1a54
|
||||
#define AR_MCI_LAST_HW_MSG_BDY 0x1a58
|
||||
|
||||
#define AR_MCI_SCHD_TABLE_2 0x1a5c
|
||||
#define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001
|
||||
#define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0
|
||||
#define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002
|
||||
#define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1
|
||||
|
||||
#define AR_BTCOEX_CTRL3 0x1a60
|
||||
#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff
|
||||
#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue