ARM: S3C24XX: use clk_get_rate to init fclk in common_setup_clocks
Previously the fclk rate was calculated by dividing the pll through the divider value of the armdiv. With a real armdiv clk in place it's possible to simply read its value, which does essentially the same. This change makes the whole fdiv_fn function pointers supplied to s3c2443_common_init_clocks and s3c2443_common_setup_clocks obsolete, so remove it too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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866a1c8c35
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4 changed files with 9 additions and 26 deletions
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@ -133,16 +133,9 @@ static struct clk hsmmc0_clk = {
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.ctrlbit = S3C2416_HCLKCON_HSMMC0,
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.ctrlbit = S3C2416_HCLKCON_HSMMC0,
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};
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};
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static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
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{
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clkcon0 &= S3C2416_CLKDIV0_ARMDIV_MASK;
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return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
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}
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void __init_or_cpufreq s3c2416_setup_clocks(void)
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void __init_or_cpufreq s3c2416_setup_clocks(void)
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{
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{
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s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
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s3c2443_common_setup_clocks(s3c2416_get_pll);
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}
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}
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@ -166,7 +159,7 @@ void __init s3c2416_init_clocks(int xtal)
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clk_epll.parent = &clk_epllref.clk;
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clk_epll.parent = &clk_epllref.clk;
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s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div,
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s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
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armdiv, ARRAY_SIZE(armdiv),
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armdiv, ARRAY_SIZE(armdiv),
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S3C2416_CLKDIV0_ARMDIV_MASK);
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S3C2416_CLKDIV0_ARMDIV_MASK);
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@ -76,13 +76,6 @@ static unsigned int armdiv[16] = {
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[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
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[S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
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};
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};
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static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
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{
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clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
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return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
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}
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/* hsspi
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/* hsspi
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*
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*
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* high-speed spi clock, sourced from esysclk
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* high-speed spi clock, sourced from esysclk
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@ -191,7 +184,7 @@ static struct clk *clks[] __initdata = {
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void __init_or_cpufreq s3c2443_setup_clocks(void)
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void __init_or_cpufreq s3c2443_setup_clocks(void)
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{
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{
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s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
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s3c2443_common_setup_clocks(s3c2443_get_mpll);
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}
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}
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void __init s3c2443_init_clocks(int xtal)
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void __init s3c2443_init_clocks(int xtal)
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@ -202,7 +195,7 @@ void __init s3c2443_init_clocks(int xtal)
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clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
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clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
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clk_epll.parent = &clk_epllref.clk;
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clk_epll.parent = &clk_epllref.clk;
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s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div,
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s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
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armdiv, ARRAY_SIZE(armdiv),
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armdiv, ARRAY_SIZE(armdiv),
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S3C2443_CLKDIV0_ARMDIV_MASK);
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S3C2443_CLKDIV0_ARMDIV_MASK);
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@ -520,8 +520,7 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
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/* EPLLCON compatible enough to get on/off information */
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/* EPLLCON compatible enough to get on/off information */
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void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
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void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
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fdiv_fn get_fdiv)
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{
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{
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unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
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unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
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unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
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unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
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@ -541,7 +540,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
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pll = get_mpll(mpllcon, xtal);
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pll = get_mpll(mpllcon, xtal);
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clk_msysclk.clk.rate = pll;
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clk_msysclk.clk.rate = pll;
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fclk = pll / get_fdiv(clkdiv0);
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fclk = clk_get_rate(&clk_armdiv);
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hclk = s3c2443_prediv_getrate(&clk_prediv);
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hclk = s3c2443_prediv_getrate(&clk_prediv);
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hclk /= s3c2443_get_hdiv(clkdiv0);
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hclk /= s3c2443_get_hdiv(clkdiv0);
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pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
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pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
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@ -590,7 +589,6 @@ static struct clksrc_clk *clksrcs[] __initdata = {
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};
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};
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void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
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void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
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fdiv_fn get_fdiv,
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unsigned int *divs, int nr_divs,
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unsigned int *divs, int nr_divs,
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int divmask)
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int divmask)
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{
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{
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@ -620,5 +618,5 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c2443_common_setup_clocks(get_mpll, get_fdiv);
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s3c2443_common_setup_clocks(get_mpll);
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}
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}
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@ -37,10 +37,9 @@ extern int s3c2443_baseclk_add(void);
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struct clk; /* some files don't need clk.h otherwise */
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struct clk; /* some files don't need clk.h otherwise */
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typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
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typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
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typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
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extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
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extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
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extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv,
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extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
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unsigned int *divs, int nr_divs,
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unsigned int *divs, int nr_divs,
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int divmask);
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int divmask);
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