arm64: ensure completion of TLB invalidatation
Currently there is no dsb between the tlbi in __cpu_setup and the write to SCTLR_EL1 which enables the MMU in __turn_mmu_on. This means that the TLB invalidation is not guaranteed to have completed at the point address translation is enabled, leading to a number of possible issues including incorrect translations and TLB conflict faults. This patch moves the tlbi in __cpu_setup above an existing dsb used to synchronise I-cache invalidation, ensuring that the TLBs have been invalidated at the point the MMU is enabled. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -111,12 +111,12 @@ ENTRY(__cpu_setup)
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bl __flush_dcache_all
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bl __flush_dcache_all
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mov lr, x28
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mov lr, x28
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ic iallu // I+BTB cache invalidate
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ic iallu // I+BTB cache invalidate
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tlbi vmalle1is // invalidate I + D TLBs
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dsb sy
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dsb sy
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mov x0, #3 << 20
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mov x0, #3 << 20
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msr cpacr_el1, x0 // Enable FP/ASIMD
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msr cpacr_el1, x0 // Enable FP/ASIMD
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msr mdscr_el1, xzr // Reset mdscr_el1
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msr mdscr_el1, xzr // Reset mdscr_el1
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tlbi vmalle1is // invalidate I + D TLBs
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/*
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/*
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* Memory region attributes for LPAE:
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* Memory region attributes for LPAE:
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*
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*
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