drm/radeon/kms: move disp eng pll setup to init path
We really only need to set it up once on init or resume rather than on every mode set. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
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211fa4fc4e
commit
3fa47d9efa
4 changed files with 36 additions and 33 deletions
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@ -355,15 +355,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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}
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static void atombios_disable_ss(struct drm_crtc *crtc)
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static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
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{
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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u32 ss_cntl;
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u32 ss_cntl;
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if (ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE4(rdev)) {
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switch (radeon_crtc->pll_id) {
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switch (pll_id) {
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case ATOM_PPLL1:
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case ATOM_PPLL1:
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ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
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ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
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ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
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ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
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@ -379,7 +376,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc)
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return;
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return;
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}
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}
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} else if (ASIC_IS_AVIVO(rdev)) {
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} else if (ASIC_IS_AVIVO(rdev)) {
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switch (radeon_crtc->pll_id) {
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switch (pll_id) {
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case ATOM_PPLL1:
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case ATOM_PPLL1:
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ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
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ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
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ss_cntl &= ~1;
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ss_cntl &= ~1;
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@ -406,13 +403,11 @@ union atom_enable_ss {
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ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
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ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
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};
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};
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static void atombios_crtc_program_ss(struct drm_crtc *crtc,
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static void atombios_crtc_program_ss(struct radeon_device *rdev,
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int enable,
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int enable,
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int pll_id,
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int pll_id,
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struct radeon_atom_ss *ss)
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struct radeon_atom_ss *ss)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
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int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
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union atom_enable_ss args;
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union atom_enable_ss args;
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@ -479,7 +474,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
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} else if (ASIC_IS_AVIVO(rdev)) {
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} else if (ASIC_IS_AVIVO(rdev)) {
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if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
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if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
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(ss->type & ATOM_EXTERNAL_SS_MASK)) {
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(ss->type & ATOM_EXTERNAL_SS_MASK)) {
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atombios_disable_ss(crtc);
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atombios_disable_ss(rdev, pll_id);
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return;
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return;
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}
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}
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args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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@ -491,7 +486,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
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} else {
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} else {
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if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
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if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
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(ss->type & ATOM_EXTERNAL_SS_MASK)) {
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(ss->type & ATOM_EXTERNAL_SS_MASK)) {
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atombios_disable_ss(crtc);
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atombios_disable_ss(rdev, pll_id);
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return;
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return;
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}
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}
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args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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@ -702,11 +697,9 @@ union set_pixel_clock {
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/* on DCE5, make sure the voltage is high enough to support the
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/* on DCE5, make sure the voltage is high enough to support the
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* required disp clk.
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* required disp clk.
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*/
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*/
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static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
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static void atombios_crtc_set_dcpll(struct radeon_device *rdev,
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u32 dispclk)
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u32 dispclk)
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{
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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u8 frev, crev;
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u8 frev, crev;
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int index;
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int index;
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union set_pixel_clock args;
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union set_pixel_clock args;
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@ -996,7 +989,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
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radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
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radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
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&ref_div, &post_div);
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&ref_div, &post_div);
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atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
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atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
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atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
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atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
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encoder_mode, radeon_encoder->encoder_id, mode->clock,
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encoder_mode, radeon_encoder->encoder_id, mode->clock,
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@ -1019,7 +1012,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
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ss.step = step_size;
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ss.step = step_size;
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}
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}
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atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
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atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
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}
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}
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}
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}
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@ -1494,6 +1487,24 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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}
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}
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void radeon_atom_dcpll_init(struct radeon_device *rdev)
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{
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/* always set DCPLL */
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if (ASIC_IS_DCE4(rdev)) {
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struct radeon_atom_ss ss;
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bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
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ASIC_INTERNAL_SS_ON_DCPLL,
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rdev->clock.default_dispclk);
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if (ss_enabled)
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atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
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/* XXX: DCE5, make sure voltage, dispclk is high enough */
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atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk);
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if (ss_enabled)
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atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
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}
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}
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int atombios_crtc_mode_set(struct drm_crtc *crtc,
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int atombios_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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struct drm_display_mode *adjusted_mode,
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@ -1515,19 +1526,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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}
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}
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/* always set DCPLL */
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if (ASIC_IS_DCE4(rdev)) {
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struct radeon_atom_ss ss;
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bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
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ASIC_INTERNAL_SS_ON_DCPLL,
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rdev->clock.default_dispclk);
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if (ss_enabled)
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atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
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/* XXX: DCE5, make sure voltage, dispclk is high enough */
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atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
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if (ss_enabled)
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atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
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}
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atombios_crtc_set_pll(crtc, adjusted_mode);
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atombios_crtc_set_pll(crtc, adjusted_mode);
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if (ASIC_IS_DCE4(rdev))
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if (ASIC_IS_DCE4(rdev))
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@ -959,9 +959,11 @@ int radeon_resume_kms(struct drm_device *dev)
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radeon_fbdev_set_suspend(rdev, 0);
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radeon_fbdev_set_suspend(rdev, 0);
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console_unlock();
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console_unlock();
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/* init dig PHYs */
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/* init dig PHYs, disp eng pll */
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if (rdev->is_atom_bios)
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if (rdev->is_atom_bios) {
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radeon_atom_encoder_init(rdev);
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radeon_atom_encoder_init(rdev);
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radeon_atom_dcpll_init(rdev);
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}
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/* reset hpd state */
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/* reset hpd state */
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radeon_hpd_init(rdev);
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radeon_hpd_init(rdev);
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/* blat the mode back in */
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/* blat the mode back in */
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@ -1305,9 +1305,11 @@ int radeon_modeset_init(struct radeon_device *rdev)
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return ret;
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return ret;
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}
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}
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/* init dig PHYs */
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/* init dig PHYs, disp eng pll */
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if (rdev->is_atom_bios)
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if (rdev->is_atom_bios) {
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radeon_atom_encoder_init(rdev);
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radeon_atom_encoder_init(rdev);
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radeon_atom_dcpll_init(rdev);
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}
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/* initialize hpd */
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/* initialize hpd */
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radeon_hpd_init(rdev);
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radeon_hpd_init(rdev);
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@ -484,6 +484,7 @@ extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
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extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
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extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
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extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
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extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
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extern void radeon_atom_encoder_init(struct radeon_device *rdev);
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extern void radeon_atom_encoder_init(struct radeon_device *rdev);
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extern void radeon_atom_dcpll_init(struct radeon_device *rdev);
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extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
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extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
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int action, uint8_t lane_num,
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int action, uint8_t lane_num,
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uint8_t lane_set);
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uint8_t lane_set);
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