[Blackfin] arch: Add proper SW System Reset delay sequence
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
parent
a628a8bcd8
commit
444ad82bc3
1 changed files with 12 additions and 3 deletions
|
@ -19,6 +19,11 @@
|
||||||
#define SYSCR_VAL 0x10
|
#define SYSCR_VAL 0x10
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15)
|
||||||
|
*/
|
||||||
|
#define SWRST_DELAY (5 * 15)
|
||||||
|
|
||||||
/* A system soft reset makes external memory unusable
|
/* A system soft reset makes external memory unusable
|
||||||
* so force this function into L1.
|
* so force this function into L1.
|
||||||
*/
|
*/
|
||||||
|
@ -34,11 +39,15 @@ void bfin_reset(void)
|
||||||
while (1) {
|
while (1) {
|
||||||
/* initiate system soft reset with magic 0x7 */
|
/* initiate system soft reset with magic 0x7 */
|
||||||
bfin_write_SWRST(0x7);
|
bfin_write_SWRST(0x7);
|
||||||
bfin_read_SWRST();
|
|
||||||
asm("ssync;");
|
/* Wait for System reset to actually reset, needs to be 5 SCLKs, */
|
||||||
|
/* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */
|
||||||
|
|
||||||
|
asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n"
|
||||||
|
: : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0");
|
||||||
|
|
||||||
/* clear system soft reset */
|
/* clear system soft reset */
|
||||||
bfin_write_SWRST(0);
|
bfin_write_SWRST(0);
|
||||||
bfin_read_SWRST();
|
|
||||||
asm("ssync;");
|
asm("ssync;");
|
||||||
/* issue core reset */
|
/* issue core reset */
|
||||||
asm("raise 1");
|
asm("raise 1");
|
||||||
|
|
Loading…
Reference in a new issue