drm/nv50: allow gpuobjs that aren't mapped into aperture
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
43efc9ce25
commit
5125bfd886
5 changed files with 88 additions and 29 deletions
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@ -513,8 +513,12 @@ struct drm_nouveau_private {
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int flags;
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void __iomem *mmio;
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void __iomem *ramin;
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uint32_t ramin_size;
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u32 ramin_size;
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u32 ramin_base;
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bool ramin_available;
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spinlock_t ramin_lock;
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struct nouveau_bo *vga_ram;
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@ -75,7 +75,7 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->engine;
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struct nouveau_gpuobj *gpuobj;
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struct drm_mm *pramin = NULL;
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struct drm_mm_node *ramin = NULL;
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int ret;
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NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
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@ -95,36 +95,42 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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/* Choose between global instmem heap, and per-channel private
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* instmem heap. On <NV50 allow requests for private instmem
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* to be satisfied from global heap if no per-channel area
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* available.
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*/
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if (chan) {
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NV_DEBUG(dev, "channel heap\n");
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pramin = &chan->ramin_heap;
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ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0);
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if (ramin)
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ramin = drm_mm_get_block(ramin, size, align);
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if (!ramin) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return -ENOMEM;
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}
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} else {
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NV_DEBUG(dev, "global heap\n");
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pramin = &dev_priv->ramin_heap;
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/* allocate backing pages, sets vinst */
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ret = engine->instmem.populate(dev, gpuobj, &size);
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if (ret) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return ret;
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}
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/* try and get aperture space */
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ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, align, 0);
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if (ramin)
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ramin = drm_mm_get_block(ramin, size, align);
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/* on nv50 it's ok to fail, we have a fallback path */
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if (!ramin && dev_priv->card_type < NV_50) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return -ENOMEM;
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}
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}
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/* Allocate a chunk of the PRAMIN aperture */
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gpuobj->im_pramin = drm_mm_search_free(pramin, size, align, 0);
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if (gpuobj->im_pramin)
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gpuobj->im_pramin = drm_mm_get_block(gpuobj->im_pramin, size, align);
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if (!gpuobj->im_pramin) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return -ENOMEM;
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}
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if (!chan) {
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/* if we got a chunk of the aperture, map pages into it */
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gpuobj->im_pramin = ramin;
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if (!chan && gpuobj->im_pramin) {
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ret = engine->instmem.bind(dev, gpuobj);
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if (ret) {
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nouveau_gpuobj_ref(NULL, &gpuobj);
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@ -134,7 +140,10 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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/* calculate the various different addresses for the object */
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if (chan) {
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gpuobj->pinst = gpuobj->im_pramin->start + chan->ramin->pinst;
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gpuobj->pinst = chan->ramin->pinst;
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if (gpuobj->pinst != ~0)
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gpuobj->pinst += gpuobj->im_pramin->start;
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if (dev_priv->card_type < NV_50) {
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gpuobj->cinst = gpuobj->pinst;
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} else {
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@ -143,7 +152,10 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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chan->ramin->vinst;
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}
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} else {
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gpuobj->pinst = gpuobj->im_pramin->start;
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if (gpuobj->im_pramin)
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gpuobj->pinst = gpuobj->im_pramin->start;
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else
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gpuobj->pinst = ~0;
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gpuobj->cinst = 0xdeadbeef;
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}
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@ -168,6 +180,8 @@ nouveau_gpuobj_early_init(struct drm_device *dev)
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NV_DEBUG(dev, "\n");
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INIT_LIST_HEAD(&dev_priv->gpuobj_list);
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spin_lock_init(&dev_priv->ramin_lock);
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dev_priv->ramin_base = ~0;
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return 0;
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}
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@ -650,12 +664,15 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
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* locations determined during init.
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*/
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if (dev_priv->card_type >= NV_50) {
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uint32_t vm_offset, pde;
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u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
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u64 vm_vinst = chan->ramin->vinst + pgd_offs;
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u32 vm_pinst = chan->ramin->pinst;
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u32 pde;
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vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200;
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vm_offset += chan->ramin->im_pramin->start;
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if (vm_pinst != ~0)
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vm_pinst += pgd_offs;
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ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000,
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ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000,
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0, &chan->vm_pd);
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if (ret)
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return ret;
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@ -941,11 +958,46 @@ int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
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u32
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nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
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{
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return nv_ri32(gpuobj->dev, gpuobj->pinst + offset);
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struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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struct drm_device *dev = gpuobj->dev;
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if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
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u64 ptr = gpuobj->vinst + offset;
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u32 base = ptr >> 16;
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u32 val;
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spin_lock(&dev_priv->ramin_lock);
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if (dev_priv->ramin_base != base) {
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dev_priv->ramin_base = base;
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nv_wr32(dev, 0x001700, dev_priv->ramin_base);
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}
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val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
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spin_unlock(&dev_priv->ramin_lock);
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return val;
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}
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return nv_ri32(dev, gpuobj->pinst + offset);
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}
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void
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nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
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{
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nv_wi32(gpuobj->dev, gpuobj->pinst + offset, val);
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struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
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struct drm_device *dev = gpuobj->dev;
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if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
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u64 ptr = gpuobj->vinst + offset;
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u32 base = ptr >> 16;
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spin_lock(&dev_priv->ramin_lock);
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if (dev_priv->ramin_base != base) {
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dev_priv->ramin_base = base;
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nv_wr32(dev, 0x001700, dev_priv->ramin_base);
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}
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nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
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spin_unlock(&dev_priv->ramin_lock);
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return;
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}
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nv_wi32(dev, gpuobj->pinst + offset, val);
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}
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@ -134,6 +134,7 @@ int nv04_instmem_init(struct drm_device *dev)
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return ret;
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}
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dev_priv->ramin_available = true;
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return 0;
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}
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@ -72,7 +72,7 @@ nv40_graph_create_context(struct nouveau_channel *chan)
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ctx.data = chan->ramin_grctx;
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nv40_grctx_init(&ctx);
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nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->im_pramin->start);
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nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
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return 0;
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}
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@ -249,6 +249,8 @@ nv50_instmem_init(struct drm_device *dev)
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for (i = 0; i < 8; i++)
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nv_wr32(dev, 0x1900 + (i*4), 0);
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dev_priv->ramin_available = true;
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/* Assume that praying isn't enough, check that we can re-read the
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* entire fake channel back from the PRAMIN BAR */
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for (i = 0; i < c_size; i += 4) {
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