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Pin control fixes for the v4.15 cycle:

Browse source 
- Fix the UART2 RTS pin mode on Intel Denverton.
 - Fix the direction_output() behaviour on the Armada 37xx.
 - Fix the groups selection per-SoC on the Gemini.
 - Fix the interrupt pin bank on the Sunxi A80.
 - Fix the UART mux on the Sunxi A64.
 - Disable the strict mode on the Sunxi H5 driver.
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Merge tag 'pinctrl-v4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "As with GPIO not much action in pin control. All are driver fixes:

   - fix the UART2 RTS pin mode on Intel Denverton

   - fix the direction_output() behaviour on the Armada 37xx

   - fix the groups selection per-SoC on the Gemini

   - fix the interrupt pin bank on the Sunxi A80

   - fix the UART mux on the Sunxi A64

   - disable the strict mode on the Sunxi H5 driver"

* tag 'pinctrl-v4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: sunxi: Disable strict mode for H5 driver
  pinctrl: sunxi: Fix A64 UART mux value
  pinctrl: sunxi: Fix A80 interrupt pin bank
  pinctrl: gemini: Fix usage of 3512 groups
  pinctrl: armada-37xx: Fix direction_output() callback behavior
  pinctrl: denverton: Fix UART2 RTS pin mode
This commit is contained in:
Linus Torvalds 2017-12-05 08:47:20 -08:00
commit 54b9937082
6 changed files with 21 additions and 10 deletions
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2
drivers/pinctrl/intel/pinctrl-denverton.c
View file

@ -207,7 +207,7 @@ static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
static const unsigned int dnv_uart2_modes[] = { 1, 1, 2, 2 };
static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };
static const unsigned int dnv_emmc_pins[] = {
142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
};

13
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View file

@ -408,12 +408,21 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
{
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int mask;
unsigned int mask, val, ret;
armada_37xx_update_reg(&reg, offset);
mask = BIT(offset);
return regmap_update_bits(info->regmap, reg, mask, mask);
ret = regmap_update_bits(info->regmap, reg, mask, mask);
if (ret)
return ret;
reg = OUTPUT_VAL;
val = value ? mask : 0;
regmap_update_bits(info->regmap, reg, mask, val);
return 0;
}
static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)

2
drivers/pinctrl/pinctrl-gemini.c
View file

@ -2322,7 +2322,7 @@ static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
int i;
for (i = 0; i < pmx->nconfs; i++) {
retconf = &gemini_confs_3516[i];
retconf = &pmx->confs[i];
if (retconf->pin == pin)
return retconf;
}

2
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
View file

@ -428,7 +428,7 @@ static const struct sunxi_desc_pin a64_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
SUNXI_FUNCTION(0x3, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),

6
drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
View file

@ -535,14 +535,16 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 2,
.irq_read_needs_mux = true
.irq_read_needs_mux = true,
.disable_strict_mode = true,
};
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 3,
.irq_read_needs_mux = true
.irq_read_needs_mux = true,
.disable_strict_mode = true,
};
static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)

6
drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
View file

@ -145,19 +145,19 @@ static const struct sunxi_desc_pin sun9i_a80_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "mcsi"), /* MCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PB_EINT14 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PB_EINT14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "mcsi"), /* SCK */
SUNXI_FUNCTION(0x4, "i2c4"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PB_EINT15 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PB_EINT15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "mcsi"), /* SDA */
SUNXI_FUNCTION(0x4, "i2c4"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PB_EINT16 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PB_EINT16 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),