Merge "power: qpnp-qg: Battery-temp based ESR enable"
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commit
79d09578b2
2 changed files with 21 additions and 1 deletions
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@ -59,6 +59,7 @@ struct qg_dt {
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int sys_min_volt_mv;
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int fvss_vbat_mv;
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int tcss_entry_soc;
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int esr_low_temp_threshold;
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bool hold_soc_while_full;
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bool linearize_soc;
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bool cl_disable;
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@ -1020,7 +1020,7 @@ static int qg_process_esr_data(struct qpnp_qg *chip)
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static int qg_esr_estimate(struct qpnp_qg *chip)
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{
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int rc, i, ibat = 0;
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int rc, i, ibat = 0, temp = 0;
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u8 esr_done_count, reg0 = 0, reg1 = 0;
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bool is_charging = false;
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@ -1046,6 +1046,17 @@ static int qg_esr_estimate(struct qpnp_qg *chip)
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!chip->dt.esr_discharge_enable)
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return 0;
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/* Ignore ESR if battery-temp is below a threshold */
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rc = qg_get_battery_temp(chip, &temp);
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if (rc < 0)
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return rc;
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if (temp < chip->dt.esr_low_temp_threshold) {
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qg_dbg(chip, QG_DEBUG_ESR,
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"Battery temperature(%d) below threshold(%d) for ESR\n",
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temp, chip->dt.esr_low_temp_threshold);
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return 0;
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}
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if (chip->batt_soc != INT_MIN && (chip->batt_soc <
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chip->dt.esr_disable_soc)) {
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qg_dbg(chip, QG_DEBUG_ESR,
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@ -4127,6 +4138,7 @@ static int qg_parse_cl_dt(struct qpnp_qg *chip)
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#define DEFAULT_SYS_MIN_VOLT_MV 2800
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#define DEFAULT_FVSS_VBAT_MV 3500
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#define DEFAULT_TCSS_ENTRY_SOC 90
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#define DEFAULT_ESR_LOW_TEMP_THRESHOLD 100 /* 10 deg */
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static int qg_parse_dt(struct qpnp_qg *chip)
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{
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int rc = 0;
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@ -4336,6 +4348,13 @@ static int qg_parse_dt(struct qpnp_qg *chip)
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else
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chip->dt.esr_min_ibat_ua = (int)temp;
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rc = of_property_read_u32(node, "qcom,esr-low-temp-threshold", &temp);
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if (rc < 0)
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chip->dt.esr_low_temp_threshold =
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DEFAULT_ESR_LOW_TEMP_THRESHOLD;
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else
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chip->dt.esr_low_temp_threshold = (int)temp;
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rc = of_property_read_u32(node, "qcom,shutdown_soc_threshold", &temp);
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if (rc < 0)
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chip->dt.shutdown_soc_threshold = -EINVAL;
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