clk: qcom: clk-alpha: Reconfigure Fabia PLL during enable
During enable read the L value to determine if the configuration is required again, otherwise the PLL would fail to lock or enable due to lost/missing values. Also update the PLL configuration, calibration and list register functionalities. Change-Id: Iad06657b84352915c73c509c5ef04a5f9c528598 Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das
parent
004818ff21
commit
7f9c6bce91
2 changed files with 179 additions and 5 deletions
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@ -94,6 +94,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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},
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[CLK_ALPHA_PLL_TYPE_FABIA] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_CAL_L_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_USER_CTL_U] = 0x10,
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[PLL_OFF_CONFIG_CTL] = 0x14,
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@ -167,6 +168,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define ZONDA_STAY_IN_CFA BIT(16)
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#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
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/* FABIA PLL specific settings */
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#define FABIA_PLL_CAL_VAL 0x3F
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#define pll_alpha_width(p) \
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((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
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ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
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@ -1315,14 +1319,24 @@ const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
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void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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u32 val, mask;
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if (!config) {
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pr_err("PLL configuration missing.\n");
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return -EINVAL;
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}
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if (config->l)
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regmap_write(regmap, PLL_L_VAL(pll), config->l);
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if (config->cal_l)
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regmap_write(regmap, PLL_CAL_L_VAL(pll), config->cal_l);
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else
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regmap_write(regmap, PLL_CAL_L_VAL(pll), FABIA_PLL_CAL_VAL);
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if (config->alpha)
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regmap_write(regmap, PLL_FRAC(pll), config->alpha);
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@ -1330,6 +1344,26 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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regmap_write(regmap, PLL_CONFIG_CTL(pll),
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config->config_ctl_val);
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if (config->config_ctl_hi_val)
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regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
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config->config_ctl_hi_val);
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if (config->user_ctl_val)
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regmap_write(regmap, PLL_USER_CTL(pll),
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config->user_ctl_val);
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if (config->user_ctl_hi_val)
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regmap_write(regmap, PLL_USER_CTL_U(pll),
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config->user_ctl_hi_val);
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if (config->test_ctl_val)
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regmap_write(regmap, PLL_TEST_CTL(pll),
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config->test_ctl_val);
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if (config->test_ctl_hi_val)
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regmap_write(regmap, PLL_TEST_CTL_U(pll),
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config->test_ctl_hi_val);
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if (config->post_div_mask) {
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mask = config->post_div_mask;
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val = config->post_div_val;
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@ -1340,6 +1374,7 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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PLL_UPDATE_BYPASS);
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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return 0;
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}
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EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
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@ -1347,7 +1382,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
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{
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int ret;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, opmode_val;
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u32 val, opmode_val, l_val, cal_val;
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struct regmap *regmap = pll->clkr.regmap;
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ret = regmap_read(regmap, PLL_MODE(pll), &val);
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@ -1370,6 +1405,24 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
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if ((opmode_val & PLL_OPMODE_RUN) && (val & PLL_OUTCTRL))
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return 0;
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ret = regmap_read(regmap, PLL_L_VAL(pll), &l_val);
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if (ret)
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return ret;
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ret = regmap_read(regmap, PLL_CAL_L_VAL(pll), &cal_val);
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if (ret)
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return ret;
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/* PLL has lost it's L or CAL value, needs reconfiguration */
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if (!l_val || !cal_val) {
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ret = clk_fabia_pll_configure(pll, regmap, pll->config);
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if (ret) {
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pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
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return ret;
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}
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pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");
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}
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ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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if (ret)
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return ret;
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@ -1447,15 +1500,27 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, l, alpha_width = pll_alpha_width(pll);
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u32 l, cal_val, alpha_width = pll_alpha_width(pll);
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u64 a;
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unsigned long rrate;
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int ret = 0;
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ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
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ret = regmap_read(pll->clkr.regmap, PLL_CAL_L_VAL(pll), &cal_val);
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if (ret)
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return ret;
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/* PLL has lost it's CAL value, needs reconfiguration */
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if (!cal_val) {
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ret = clk_fabia_pll_configure(pll, pll->clkr.regmap,
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pll->config);
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if (ret) {
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pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
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return ret;
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}
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pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",
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clk_hw_get_name(hw));
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}
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rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
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/*
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@ -1473,13 +1538,121 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
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return __clk_alpha_pll_update_latch(pll);
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}
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/*
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* Fabia PLL requires power-on self calibration which happen when the PLL comes
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* out of reset. Calibration frequency is calculated by below relation:
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*
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* calibration freq = ((pll_l_valmax + pll_l_valmin) * 0.54)
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*/
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static int alpha_pll_fabia_prepare(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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const struct pll_vco *vco;
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struct clk_hw *parent;
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unsigned long calibration_freq, freq_hz;
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u32 l, alpha_width = pll_alpha_width(pll), regval;
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u64 a;
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int ret;
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/* Check if calibration needs to be done i.e. PLL is in reset */
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ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val);
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if (ret)
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return ret;
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/* Return early if calibration is not needed. */
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if (regval & PLL_RESET_N)
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return 0;
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vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
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if (!vco) {
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pr_err("alpha pll: not in a valid vco range\n");
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return -EINVAL;
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}
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calibration_freq = ((pll->vco_table[0].min_freq +
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pll->vco_table[0].max_freq) * 54)/100;
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parent = clk_hw_get_parent(hw);
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if (!parent)
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return -EINVAL;
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freq_hz = alpha_pll_round_rate(calibration_freq,
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clk_hw_get_rate(parent), &l, &a, alpha_width);
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/*
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* Due to a limited number of bits for fractional rate programming, the
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* rounded up rate could be marginally higher than the requested rate.
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*/
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if (freq_hz > (calibration_freq + PLL_OUT_RATE_MARGIN) ||
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freq_hz < calibration_freq)
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return -EINVAL;
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/* Setup PLL for calibration frequency */
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regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), FABIA_PLL_CAL_VAL);
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/* Bringup the pll at calibration frequency */
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ret = alpha_pll_fabia_enable(hw);
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if (ret) {
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pr_err("alpha pll calibration failed\n");
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return ret;
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}
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alpha_pll_fabia_disable(hw);
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return 0;
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}
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static void clk_fabia_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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int size, i, val;
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static struct clk_register_data data[] = {
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{"PLL_MODE", PLL_OFF_MODE},
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{"PLL_L_VAL", PLL_OFF_L_VAL},
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{"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL},
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{"PLL_USER_CTL", PLL_OFF_USER_CTL},
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{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},
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{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},
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{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},
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{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},
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{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},
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{"PLL_STATUS", PLL_OFF_STATUS},
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{"PLL_OPMODE", PLL_OFF_MODE},
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{"PLL_FRAC", PLL_OFF_FRAC},
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};
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static struct clk_register_data data1[] = {
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{"APSS_PLL_VOTE", 0x0},
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};
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size = ARRAY_SIZE(data);
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for (i = 0; i < size; i++) {
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regmap_read(pll->clkr.regmap, pll->offset +
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pll->regs[data[i].offset], &val);
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clock_debug_output(f, false,
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"%20s: 0x%.8x\n", data[i].name, val);
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}
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regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],
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&val);
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if (val & PLL_FSM_ENA) {
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regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
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data1[0].offset, &val);
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clock_debug_output(f, false,
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"%20s: 0x%.8x\n", data1[0].name, val);
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}
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}
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const struct clk_ops clk_alpha_pll_fabia_ops = {
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.prepare = alpha_pll_fabia_prepare,
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.enable = alpha_pll_fabia_enable,
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.disable = alpha_pll_fabia_disable,
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.is_enabled = clk_alpha_pll_is_enabled,
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.set_rate = alpha_pll_fabia_set_rate,
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.recalc_rate = alpha_pll_fabia_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.list_registers = clk_fabia_pll_list_registers,
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.bus_vote = clk_debug_bus_vote,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
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@ -1490,6 +1663,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
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.is_enabled = clk_alpha_pll_is_enabled,
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.recalc_rate = alpha_pll_fabia_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.list_registers = clk_fabia_pll_list_registers,
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.bus_vote = clk_debug_bus_vote,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
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@ -141,7 +141,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_zonda_ops;
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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