dmaengine: PL08x: extract function to to generate cctl values

Extract the functionality from dma_slave_config to generate the cctl
values for a given bus width and burst size.  This allows us to use
this elsewhere in the driver, namely the prepare functions.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2012-05-16 11:16:03 +01:00
parent 409ec8db46
commit 9862ba17b7

View file

@ -1207,14 +1207,40 @@ static u32 pl08x_burst(u32 maxburst)
return burst_sizes[i].reg;
}
static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
enum dma_slave_buswidth addr_width, u32 maxburst)
{
u32 width, burst, cctl = 0;
width = pl08x_width(addr_width);
if (width == ~0)
return ~0;
cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
/*
* If this channel will only request single transfers, set this
* down to ONE element. Also select one element if no maxburst
* is specified.
*/
if (plchan->cd->single)
maxburst = 1;
burst = pl08x_burst(maxburst);
cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
return pl08x_cctl(cctl);
}
static int dma_set_runtime_config(struct dma_chan *chan,
struct dma_slave_config *config)
{
struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
struct pl08x_driver_data *pl08x = plchan->host;
enum dma_slave_buswidth addr_width;
u32 width, burst, maxburst;
u32 cctl = 0;
u32 maxburst, cctl = 0;
if (!plchan->slave)
return -EINVAL;
@ -1233,8 +1259,8 @@ static int dma_set_runtime_config(struct dma_chan *chan,
return -EINVAL;
}
width = pl08x_width(addr_width);
if (width == ~0) {
cctl = pl08x_get_cctl(plchan, addr_width, maxburst);
if (cctl == ~0) {
dev_err(&pl08x->adev->dev,
"bad runtime_config: alien address width\n");
return -EINVAL;
@ -1242,25 +1268,10 @@ static int dma_set_runtime_config(struct dma_chan *chan,
plchan->cfg = *config;
cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
/*
* If this channel will only request single transfers, set this
* down to ONE element. Also select one element if no maxburst
* is specified.
*/
if (plchan->cd->single)
maxburst = 1;
burst = pl08x_burst(maxburst);
cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
plchan->src_cctl = pl08x_cctl(cctl);
plchan->src_cctl = cctl;
} else {
plchan->dst_cctl = pl08x_cctl(cctl);
plchan->dst_cctl = cctl;
}
dev_dbg(&pl08x->adev->dev,