ARM: 6388/1: errata: DMB operation may be faulty
On versions of the Cortex-A9 up to and including r2p2, under rare circumstances, a DMB instruction between 2 write operations may not ensure the correct visibility ordering of the 2 writes. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing the DMB instruction to behave like a DSB, which functions correctly on the affected cores. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2 changed files with 26 additions and 2 deletions
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@ -1051,6 +1051,18 @@ config ARM_ERRATA_460075
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ACTLR register. Note that setting specific bits in the ACTLR register
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ACTLR register. Note that setting specific bits in the ACTLR register
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may not be available in non-secure mode.
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may not be available in non-secure mode.
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config ARM_ERRATA_742230
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bool "ARM errata: DMB operation may be faulty"
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depends on CPU_V7 && SMP
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help
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This option enables the workaround for the 742230 Cortex-A9
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(r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
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between two write operations may not ensure the correct visibility
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ordering of the two writes. This workaround sets a specific bit in
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the diagnostic register of the Cortex-A9 which causes the DMB
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instruction to behave as a DSB, ensuring the correct behaviour of
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the two writes.
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config PL310_ERRATA_588369
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config PL310_ERRATA_588369
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bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
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bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
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depends on CACHE_L2X0 && ARCH_OMAP4
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depends on CACHE_L2X0 && ARCH_OMAP4
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@ -201,7 +201,7 @@ __v7_setup:
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r10, r0, #0xff000000 @ ARM?
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and r10, r0, #0xff000000 @ ARM?
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teq r10, #0x41000000
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teq r10, #0x41000000
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bne 2f
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bne 3f
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and r5, r0, #0x00f00000 @ variant
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and r5, r0, #0x00f00000 @ variant
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and r6, r0, #0x0000000f @ revision
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and r6, r0, #0x0000000f @ revision
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orr r6, r6, r5, lsr #20-4 @ combine variant and revision
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orr r6, r6, r5, lsr #20-4 @ combine variant and revision
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@ -231,8 +231,20 @@ __v7_setup:
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orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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#endif
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b 3f
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2: mov r10, #0
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/* Cortex-A9 Errata */
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2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
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teq r0, r10
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bne 3f
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#ifdef CONFIG_ARM_ERRATA_742230
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cmp r6, #0x22 @ only present up to r2p2
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mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrle r10, r10, #1 << 4 @ set bit #4
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mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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3: mov r10, #0
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#ifdef HARVARD_CACHE
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#ifdef HARVARD_CACHE
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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#endif
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#endif
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