Merge "msm: npu: Send IPCC irq directly while apps crashes"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
a0c52ad452
4 changed files with 239 additions and 5 deletions
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _NPU_COMMON_H
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@ -341,5 +341,7 @@ int load_fw(struct npu_device *npu_dev);
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int unload_fw(struct npu_device *npu_dev);
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int npu_set_bw(struct npu_device *npu_dev, int new_ib, int new_ab);
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int npu_process_kevent(struct npu_client *client, struct npu_kevent *kevt);
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int npu_notify_cdsprm_cxlimit_activity(struct npu_device *npu_dev, bool enable);
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int npu_bridge_mbox_send_data(struct npu_host_ctx *host_ctx,
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struct npu_mbox *mbox, void *data);
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#endif /* _NPU_COMMON_H */
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@ -17,6 +17,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/thermal.h>
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#include <linux/soc/qcom/llcc-qcom.h>
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#include <linux/soc/qcom/cdsprm_cxlimit.h>
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#include <soc/qcom/devfreq_devbw.h>
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#include "npu_common.h"
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@ -111,7 +112,8 @@ static int npu_pm_suspend(struct device *dev);
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static int npu_pm_resume(struct device *dev);
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static int __init npu_init(void);
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static void __exit npu_exit(void);
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static uint32_t npu_notify_cdsprm_cxlimit_corner(struct npu_device *npu_dev,
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uint32_t pwr_lvl);
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/* -------------------------------------------------------------------------
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* File Scope Variables
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* -------------------------------------------------------------------------
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@ -387,6 +389,168 @@ static ssize_t boot_store(struct device *dev,
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* Power Related
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* -------------------------------------------------------------------------
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*/
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static enum npu_power_level cdsprm_corner_to_npu_power_level(
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enum cdsprm_npu_corner corner)
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{
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enum npu_power_level pwr_lvl = NPU_PWRLEVEL_TURBO_L1;
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switch (corner) {
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case CDSPRM_NPU_CLK_OFF:
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pwr_lvl = NPU_PWRLEVEL_OFF;
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break;
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case CDSPRM_NPU_MIN_SVS:
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pwr_lvl = NPU_PWRLEVEL_MINSVS;
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break;
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case CDSPRM_NPU_LOW_SVS:
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pwr_lvl = NPU_PWRLEVEL_LOWSVS;
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break;
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case CDSPRM_NPU_SVS:
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pwr_lvl = NPU_PWRLEVEL_SVS;
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break;
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case CDSPRM_NPU_SVS_L1:
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pwr_lvl = NPU_PWRLEVEL_SVS_L1;
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break;
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case CDSPRM_NPU_NOM:
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pwr_lvl = NPU_PWRLEVEL_NOM;
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break;
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case CDSPRM_NPU_NOM_L1:
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pwr_lvl = NPU_PWRLEVEL_NOM_L1;
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break;
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case CDSPRM_NPU_TURBO:
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pwr_lvl = NPU_PWRLEVEL_TURBO;
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break;
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case CDSPRM_NPU_TURBO_L1:
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default:
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pwr_lvl = NPU_PWRLEVEL_TURBO_L1;
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break;
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}
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return pwr_lvl;
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}
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static enum cdsprm_npu_corner npu_power_level_to_cdsprm_corner(
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enum npu_power_level pwr_lvl)
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{
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enum cdsprm_npu_corner corner = CDSPRM_NPU_MIN_SVS;
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switch (pwr_lvl) {
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case NPU_PWRLEVEL_OFF:
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corner = CDSPRM_NPU_CLK_OFF;
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break;
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case NPU_PWRLEVEL_MINSVS:
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corner = CDSPRM_NPU_MIN_SVS;
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break;
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case NPU_PWRLEVEL_LOWSVS:
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corner = CDSPRM_NPU_LOW_SVS;
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break;
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case NPU_PWRLEVEL_SVS:
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corner = CDSPRM_NPU_SVS;
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break;
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case NPU_PWRLEVEL_SVS_L1:
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corner = CDSPRM_NPU_SVS_L1;
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break;
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case NPU_PWRLEVEL_NOM:
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corner = CDSPRM_NPU_NOM;
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break;
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case NPU_PWRLEVEL_NOM_L1:
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corner = CDSPRM_NPU_NOM_L1;
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break;
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case NPU_PWRLEVEL_TURBO:
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corner = CDSPRM_NPU_TURBO;
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break;
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case NPU_PWRLEVEL_TURBO_L1:
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default:
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corner = CDSPRM_NPU_TURBO_L1;
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break;
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}
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return corner;
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}
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static int npu_set_cdsprm_corner_limit(enum cdsprm_npu_corner corner)
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{
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struct npu_pwrctrl *pwr;
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enum npu_power_level pwr_lvl;
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if (!g_npu_dev)
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return 0;
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pwr = &g_npu_dev->pwrctrl;
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pwr_lvl = cdsprm_corner_to_npu_power_level(corner);
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pwr->cdsprm_pwrlevel = pwr_lvl;
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NPU_DBG("power level from cdsp %d\n", pwr_lvl);
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return npu_set_power_level(g_npu_dev, false);
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}
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const struct cdsprm_npu_limit_cbs cdsprm_npu_limit_cbs = {
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.set_corner_limit = npu_set_cdsprm_corner_limit,
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};
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int npu_notify_cdsprm_cxlimit_activity(struct npu_device *npu_dev, bool enable)
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{
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if (!npu_dev->cxlimit_registered)
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return 0;
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NPU_DBG("notify cxlimit %s activity\n", enable ? "enable" : "disable");
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return cdsprm_cxlimit_npu_activity_notify(enable ? 1 : 0);
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}
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static uint32_t npu_notify_cdsprm_cxlimit_corner(
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struct npu_device *npu_dev, uint32_t pwr_lvl)
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{
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uint32_t corner, pwr_lvl_to_set;
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if (!npu_dev->cxlimit_registered)
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return pwr_lvl;
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corner = npu_power_level_to_cdsprm_corner(pwr_lvl);
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corner = cdsprm_cxlimit_npu_corner_notify(corner);
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pwr_lvl_to_set = cdsprm_corner_to_npu_power_level(corner);
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NPU_DBG("Notify cdsprm %d:%d\n", pwr_lvl,
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pwr_lvl_to_set);
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return pwr_lvl_to_set;
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}
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int npu_cdsprm_cxlimit_init(struct npu_device *npu_dev)
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{
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bool enabled;
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int ret = 0;
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enabled = of_property_read_bool(npu_dev->pdev->dev.of_node,
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"qcom,npu-cxlimit-enable");
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NPU_DBG("qcom,npu-xclimit-enable is %s\n", enabled ? "true" : "false");
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npu_dev->cxlimit_registered = false;
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if (enabled) {
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ret = cdsprm_cxlimit_npu_limit_register(&cdsprm_npu_limit_cbs);
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if (ret) {
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NPU_ERR("register cxlimit npu limit failed\n");
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} else {
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NPU_DBG("register cxlimit npu limit succeeds\n");
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npu_dev->cxlimit_registered = true;
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}
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}
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return ret;
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}
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int npu_cdsprm_cxlimit_deinit(struct npu_device *npu_dev)
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{
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int ret = 0;
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if (npu_dev->cxlimit_registered) {
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ret = cdsprm_cxlimit_npu_limit_deregister();
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if (ret)
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NPU_ERR("deregister cxlimit npu limit failed\n");
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npu_dev->cxlimit_registered = false;
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}
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return ret;
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}
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int npu_enable_core_power(struct npu_device *npu_dev)
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{
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struct npu_pwrctrl *pwr = &npu_dev->pwrctrl;
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@ -530,6 +694,11 @@ int npu_set_power_level(struct npu_device *npu_dev, bool notify_cxlimit)
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return 0;
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}
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/* notify cxlimit to get allowed power level */
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if ((pwr_level_to_set > pwr->active_pwrlevel) && notify_cxlimit)
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pwr_level_to_set = npu_notify_cdsprm_cxlimit_corner(
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npu_dev, pwr_level_to_cdsprm);
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pwr_level_to_set = min(pwr_level_to_set,
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npu_dev->pwrctrl.cdsprm_pwrlevel);
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@ -596,6 +765,12 @@ int npu_set_power_level(struct npu_device *npu_dev, bool notify_cxlimit)
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ret = 0;
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}
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if ((pwr_level_to_cdsprm < pwr->active_pwrlevel) && notify_cxlimit) {
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npu_notify_cdsprm_cxlimit_corner(npu_dev,
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pwr_level_to_cdsprm);
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NPU_DBG("Notify cdsprm(post) %d\n", pwr_level_to_cdsprm);
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}
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pwr->active_pwrlevel = pwr_level_to_set;
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return ret;
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}
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@ -708,6 +883,13 @@ static int npu_enable_clocks(struct npu_device *npu_dev, bool post_pil)
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uint32_t pwrlevel_to_set, pwrlevel_idx;
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pwrlevel_to_set = pwr->active_pwrlevel;
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if (!post_pil) {
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pwrlevel_to_set = npu_notify_cdsprm_cxlimit_corner(
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npu_dev, pwrlevel_to_set);
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NPU_DBG("Notify cdsprm %d\n", pwrlevel_to_set);
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pwr->active_pwrlevel = pwrlevel_to_set;
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}
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pwrlevel_idx = npu_power_level_to_index(npu_dev, pwrlevel_to_set);
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pwrlevel = &pwr->pwrlevels[pwrlevel_idx];
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for (i = 0; i < npu_dev->core_clk_num; i++) {
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@ -775,6 +957,11 @@ static void npu_disable_clocks(struct npu_device *npu_dev, bool post_pil)
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int i, rc = 0;
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struct npu_clk *core_clks = npu_dev->core_clks;
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if (!post_pil) {
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npu_notify_cdsprm_cxlimit_corner(npu_dev, NPU_PWRLEVEL_OFF);
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NPU_DBG("Notify cdsprm clock off\n");
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}
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for (i = npu_dev->core_clk_num - 1; i >= 0 ; i--) {
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if (post_pil) {
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if (!npu_is_post_clock(core_clks[i].clk_name))
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@ -2012,6 +2199,10 @@ static int npu_ipcc_bridge_mbox_send_data(struct mbox_chan *chan, void *data)
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queue_work(host_ctx->wq, &host_ctx->bridge_mbox_work);
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spin_unlock_irqrestore(&host_ctx->bridge_mbox_lock, flags);
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if (host_ctx->app_crashed)
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npu_bridge_mbox_send_data(host_ctx,
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ipcc_mbox_chan->npu_mbox, NULL);
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return 0;
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}
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@ -2459,10 +2650,15 @@ static int npu_probe(struct platform_device *pdev)
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thermal_cdev_update(tcdev);
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}
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rc = npu_cdsprm_cxlimit_init(npu_dev);
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if (rc)
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goto error_driver_init;
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g_npu_dev = npu_dev;
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return rc;
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error_driver_init:
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npu_cdsprm_cxlimit_deinit(npu_dev);
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if (npu_dev->tcdev)
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thermal_cooling_device_unregister(npu_dev->tcdev);
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sysfs_remove_group(&npu_dev->device->kobj, &npu_fs_attr_group);
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@ -2487,6 +2683,7 @@ static int npu_remove(struct platform_device *pdev)
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npu_dev = platform_get_drvdata(pdev);
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npu_host_deinit(npu_dev);
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npu_debugfs_deinit(npu_dev);
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npu_cdsprm_cxlimit_deinit(npu_dev);
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if (npu_dev->tcdev)
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thermal_cooling_device_unregister(npu_dev->tcdev);
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sysfs_remove_group(&npu_dev->device->kobj, &npu_fs_attr_group);
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@ -672,6 +672,25 @@ static int npu_notifier_cb(struct notifier_block *this, unsigned long code,
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return ret;
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}
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static int npu_panic_handler(struct notifier_block *this,
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unsigned long event, void *ptr)
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{
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int i;
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struct npu_host_ctx *host_ctx =
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container_of(this, struct npu_host_ctx, panic_nb);
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struct npu_device *npu_dev = host_ctx->npu_dev;
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NPU_INFO("Apps crashed\n");
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for (i = 0; i < NPU_MAX_MBOX_NUM; i++)
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if (npu_dev->mbox[i].send_data_pending)
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npu_bridge_mbox_send_data(host_ctx,
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&npu_dev->mbox[i], NULL);
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host_ctx->app_crashed = true;
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return NOTIFY_DONE;
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}
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static void npu_update_pwr_work(struct work_struct *work)
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{
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int ret;
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@ -724,6 +743,14 @@ int npu_host_init(struct npu_device *npu_dev)
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goto fail;
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}
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host_ctx->panic_nb.notifier_call = npu_panic_handler;
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ret = atomic_notifier_chain_register(&panic_notifier_list,
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&host_ctx->panic_nb);
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if (ret) {
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NPU_ERR("register panic notifier failed\n");
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goto fail;
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}
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host_ctx->wq = create_workqueue("npu_general_wq");
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host_ctx->wq_pri =
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alloc_workqueue("npu_ipc_wq", WQ_HIGHPRI | WQ_UNBOUND, 0);
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@ -1104,7 +1131,7 @@ static void npu_disable_fw_work(struct work_struct *work)
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NPU_DBG("Exit disable fw work\n");
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}
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static int npu_bridge_mbox_send_data(struct npu_host_ctx *host_ctx,
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int npu_bridge_mbox_send_data(struct npu_host_ctx *host_ctx,
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struct npu_mbox *mbox, void *data)
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{
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NPU_DBG("Generating IRQ for client_id: %u; signal_id: %u\n",
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@ -2697,6 +2724,9 @@ int32_t npu_host_exec_network_v2(struct npu_client *client,
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return -EINVAL;
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}
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if (atomic_inc_return(&host_ctx->network_execute_cnt) == 1)
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npu_notify_cdsprm_cxlimit_activity(npu_dev, true);
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if (!network->is_active) {
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NPU_ERR("network is not active\n");
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ret = -EINVAL;
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@ -2847,6 +2877,9 @@ exec_v2_done:
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host_error_hdlr(npu_dev, true);
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}
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if (atomic_dec_return(&host_ctx->network_execute_cnt) == 0)
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npu_notify_cdsprm_cxlimit_activity(npu_dev, false);
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return ret;
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}
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@ -126,13 +126,15 @@ struct npu_host_ctx {
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uint32_t fw_dbg_mode;
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uint32_t exec_flags_override;
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atomic_t ipc_trans_id;
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atomic_t network_exeute_cnt;
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atomic_t network_execute_cnt;
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uint32_t err_irq_sts;
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uint32_t wdg_irq_sts;
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bool fw_error;
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bool cancel_work;
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bool app_crashed;
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struct notifier_block nb;
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struct notifier_block panic_nb;
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void *notif_hdle;
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spinlock_t bridge_mbox_lock;
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bool bridge_mbox_pwr_on;
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