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mmi_chrg_manager: optimize thermal mitigation logic

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-1, optimize thremal logic
-2, force pmic charging when the battery capacity is high(upper 90%)

Change-Id: Ic8b6a58decf4903b757c1554efe587100b69236e
Signed-off-by: xuwt2 <xuwt2@lenovo.com>
Reviewed-on: https://gerrit.mot.com/1413367
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Jianqi Yang <yangj@motorola.com>
Submit-Approved: Jira Key
Reviewed-on: https://gerrit.mot.com/1893553
Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
Reviewed-by: Wei Xu <xuwei9@lenovo.com>
This commit is contained in:
xuwt2 2019-08-30 17:51:31 +08:00 committed by Wei Xu
parent 312d45b3df
commit a2f329a62a
3 changed files with 30 additions and 6 deletions
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1
drivers/power/mmi_parallel_charger/mmi_charger_core.c
View file

@ -905,6 +905,7 @@ void clear_chg_manager(struct mmi_charger_manager *chip)
chip->pd_curr_max = pd_curr_max_init;
chip->recovery_pmic_chrg = false;
chip->thermal_mitigation_doing = false;
chip->thermal_force_pmic_chrg = false;
chip->thermal_cooling = false;
chip->thermal_cooling_cnt = 0;
chip->pd_pps_support = false;

1
drivers/power/mmi_parallel_charger/mmi_charger_core.h
View file

@ -192,6 +192,7 @@ struct mmi_charger_manager {
bool extrn_sense;
bool recovery_pmic_chrg;
bool thermal_mitigation_doing;
bool thermal_force_pmic_chrg;
bool thermal_cooling;
int thermal_cooling_cnt;

34
drivers/power/mmi_parallel_charger/mmi_charger_pump_policy.c
View file

@ -269,12 +269,14 @@ static void chrg_policy_error_recovery(struct mmi_charger_manager *chip,
#define COOLING_MAX_CNT 5
#define PPS_SELECT_PDO_RETRY_COUNT 3
#define DISABLE_CHRG_LIMIT -1
#define CP_CHRG_SOC_LIMIT 90
static void mmi_chrg_sm_work_func(struct work_struct *work)
{
struct mmi_charger_manager *chip = container_of(work,
struct mmi_charger_manager, mmi_chrg_sm_work.work);
int i = 0, rc = 0;
int ibatt_curr = 0, vbatt_volt = 0, batt_temp = 0, vbus_pres = 0;
int batt_soc = 0;
int heartbeat_dely_ms = 0;
int cooling_curr = 0;
int cooling_volt = 0;
@ -314,6 +316,11 @@ static void mmi_chrg_sm_work_func(struct work_struct *work)
if (!rc)
batt_temp = prop.intval / 10;
rc = power_supply_get_property(chip->batt_psy,
POWER_SUPPLY_PROP_CAPACITY, &prop);
if (!rc)
batt_soc = prop.intval;
if (ibatt_curr < 0)
ibatt_curr *= -1;
@ -348,6 +355,7 @@ static void mmi_chrg_sm_work_func(struct work_struct *work)
mmi_chrg_info(chip, "battery current %d\n", ibatt_curr);
mmi_chrg_info(chip, "battery voltage %d\n", vbatt_volt);
mmi_chrg_info(chip, "battery temp %d\n", batt_temp);
mmi_chrg_info(chip, "battery capacity %d\n", batt_soc);
if (vbus_pres) {
// mmi_dump_charger_error(chip, chrg_list->chrg_dev[CP_MASTER]);
@ -426,7 +434,8 @@ static void mmi_chrg_sm_work_func(struct work_struct *work)
&& vbatt_volt > chip->pl_chrg_vbatt_min
&& chrg_step->pres_chrg_step != chip->chrg_step_nums - 1
&& chrg_step->chrg_step_cc_curr >=
chrg_list->chrg_dev[CP_MASTER]->charging_curr_min) {
chrg_list->chrg_dev[CP_MASTER]->charging_curr_min
&& batt_soc < CP_CHRG_SOC_LIMIT) {
mmi_chrg_dbg(chip, PR_MOTO, "Enter into CHRG PUMP, "
"vbatt %d uV, "
@ -513,7 +522,8 @@ static void mmi_chrg_sm_work_func(struct work_struct *work)
&& vbatt_volt > chip->pl_chrg_vbatt_min
&& chrg_step->pres_chrg_step != chip->chrg_step_nums - 1
&& !chip->recovery_pmic_chrg
&& !chip->thermal_mitigation_doing) {
&& !chip->thermal_force_pmic_chrg
&& batt_soc < CP_CHRG_SOC_LIMIT) {
mmi_chrg_info(chip, "Enter CP, the reason is : "
"pd pps support %d, "
"vbatt %duV, chrg step %d\n",
@ -1245,14 +1255,19 @@ schedule:
if (chip->system_thermal_level == 0) {
chip->thermal_mitigation_doing = false;
} else if (chip->system_thermal_level == chip->thermal_levels) {
chip->thermal_force_pmic_chrg = false;
} else if ((chip->system_thermal_level == chip->thermal_levels - 1)
&& !chip->thermal_force_pmic_chrg) {
chip->thermal_mitigation_doing = true;
chip->thermal_force_pmic_chrg = true;
mmi_chrg_sm_move_state(chip, PM_STATE_SW_ENTRY);
mmi_chrg_info(chip, "Thermal is the highest, level %d, "
"Force enter into single pmic charging !\n",
chip->system_thermal_level);
} else if (chip->system_thermal_level > 0) {
} else if (chip->system_thermal_level > 0 &&
(sm_state == PM_STATE_CP_CC_LOOP ||
sm_state == PM_STATE_CP_CV_LOOP)) {
mmi_chrg_dbg(chip, PR_MOTO, "Thermal level is %d\n",
chip->system_thermal_level);
@ -1290,7 +1305,10 @@ schedule:
"pd target curr %dmA, "
"thermal level %d, "
"thermal volt %dmV, "
"thermal curr %dmA\n",
"thermal curr %dmA, "
"thermal cooling %d, "
"thermal mitigation %d, "
"thermal force pmic chrg %d\n",
pm_state_str[sm_state],
chip->pd_request_volt,
chip->pd_request_curr,
@ -1298,7 +1316,11 @@ schedule:
chip->pd_target_curr,
chip->system_thermal_level,
chip->pd_thermal_volt,
chip->pd_thermal_curr);
chip->pd_thermal_curr,
chip->thermal_cooling,
chip->thermal_mitigation_doing,
chip->thermal_force_pmic_chrg);
chip->pps_result = usbpd_select_pdo(chip->pd_handle,
chip->mmi_pd_pdo_idx,
chip->pd_target_volt,